Top Tech Jobs & Startup Jobs

Lead high-speed IC package development from concept through tapeout. Develop C4 and BGA ball maps, netlist mappings, die placement, padstacks, connectivity, and package requirement documents. Optimize package designs for signal and power integrity, manufacturability, reliability, thermal and mechanical constraints, and cost. Collaborate with chip, board, architecture, manufacturing, and simulation teams while contributing to design tools, processes, libraries, and automation.

Develop and lead automated test equipment solutions for semiconductor chip characterization, production, and wafer sort. Design high-speed test hardware, create test plans, convert simulation patterns to ATE formats, optimize test flows and yields, and release production test programs. Collaborate with design, DFX, and product engineering teams to ensure testability and customer specification compliance.

Supports FP&A for Operations by managing budgeting, forecasting, variance analysis, financial modeling, reporting, and capital expenditure forecasting. Partners with Operations leaders and cross-functional teams to provide recommendations, track purchasing cycles, ensure reporting accuracy, and improve financial processes through automation.

Design and verify digital ICs for high-speed PAM and coherent DSPs and PHYs. Perform HDL design, DFT, synthesis, static timing, power analysis, and scripting with TCL, Perl, Python, and Unix shell. Optimize and simulate parallel DSP architectures, analyze design challenges, and collaborate with architecture, validation, and software teams in an international environment.

Design and simulate high-performance analog integrated circuits for electrical and electro-optical interfaces operating at 100+ Gb/s. The intern will use Cadence and advanced technology nodes, gain experience in analog and high-speed layout, learn CMOS process and fabrication techniques, and collaborate with engineering teams on AI and cloud data center applications. This is a six-month contract in Pavia, Italy, suitable for an industrial Master Thesis.

Supports semiconductor process development for 2.5D/3D chip-on-wafer assembly and co-packaged optics. Tracks and analyzes packaging-build data, identifies NPI risks, documents mitigation plans, and summarizes technical progress. Collaborates with foundry and OSAT partners on manufacturing readiness, reliability, design-for-manufacturing, and cost tradeoffs.

Build data infrastructure for AI research involving semiconductor chip design datasets. Responsibilities include collecting, cleaning, normalizing, sanitizing, parsing, and transforming structured and semi-structured data; developing Python and SQL pipelines; navigating codebases and filesystems; collaborating with researchers to create model-ready datasets; and documenting data sources, transformations, and dataset versions.

Design Verification Interns will develop simulation environments, automated tests, and testbenches for semiconductor processors and SoCs. Responsibilities include analyzing coverage metrics, debugging failed simulations and hardware/software interactions, verifying RTL integration, and collaborating with architects and designers. The role provides hands-on experience with pre-silicon verification, UVM methodology, and industry-standard EDA tools across cloud, AI, storage, and networking chip designs.

Design, simulate, verify, and bring up analog and mixed-signal circuit blocks across the full design flow. Work on production IP including SerDes, Silicon Photonics, ADC/DAC, PLL, clock, LDO, and precision analog circuits in advanced CMOS processes. Collaborate with layout engineers, participate in design reviews, present research and design results, and complete a structured analog design curriculum.

Intern will perform synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure for complex ASIC and processor logic blocks. Responsibilities include scripting in Python, TCL, Perl, and Shell; debugging design violations with EDA tools; and collaborating with RTL, synthesis, and design teams to resolve congestion and timing bottlenecks. The role supports designs meeting performance, power, and area requirements.