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The Senior Director of Product Line Management will drive product strategy and design wins for silicon photonics solutions, collaborating across teams to ensure market success.

Monitor CCTV, access control, and alarm systems in a 24/7 Operations Center; triage and log alerts; escalate incidents to Facilities, HR, or emergency services; perform shift handoffs; operate multiple monitoring and mass-notification tools; and accurately document incidents in real time.

Lead and manage a semiconductor physical design team responsible for SoC/ASIC physical implementation. Oversee place-and-route, timing closure, ECOs, cross-functional coordination with RTL, verification, and backend teams; set priorities, mentor engineers, and drive delivery of tapeout-ready designs while ensuring compliance with export-controlled technology access requirements.

The Senior Staff Engineer will design and implement embedded firmware for high-speed optical components, collaborate with hardware teams, and optimize firmware performance while conducting design reviews and debugging efforts.

Lead design verification, emulation and post-silicon validation for complex multi-chiplet SoCs. Define verification scope, methodology, testbench architectures, timelines and tools. Collaborate cross-functionally (Architecture, Design, DFT, PD, Firmware, system teams), drive productivity improvements, hire and develop a high-performing verification team, and monitor industry DV trends to ensure successful tape-outs.

Develop and maintain UVM/SystemVerilog SoC-level verification environments, create test plans and tests to meet coverage goals, debug failures with designers, and mentor junior engineers. Work involves verification tool usage, regression setup, and scripting for automation.

Lead end-to-end chip/chiplet programs from architecture through tapeout. Define micro-architecture, oversee RTL development, verification, DFT, emulation, physical implementation, and post-Si debug. Coordinate cross-functional teams, mentor engineers, and ensure performance, power, scalability, and industry compliance for datacenter-focused chips.

Support and maintain AMS simulation environments for FinFET and BiCMOS high-speed designs. Work with analog designers, EDA vendors, TCAD/foundry teams to debug models, define QA flows, benchmark tools, create automation scripts, and develop custom circuit checks to improve simulation and verification efficiency.

Lead development of front-end ASIC design flows and methodologies to enable early detection of physical/timing issues, collaborate with architecture, RTL, and back-end teams, provide high-quality constraints, and drive delivery of timing-critical SoC designs with focus on synthesis, STA, CDC/RDC, and power/timing closure.

Support and maintain analog/mixed-signal (AMS) simulation environments for FinFET and BiCMOS high-speed designs. Collaborate with analog designers, EDA vendors, TCAD and foundry teams to debug device/circuit modeling issues, evaluate AMS tools, define custom circuit checks and model QA flows, and create automation scripts to improve verification efficiency.