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3 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Semiconductor
The role involves working on physical design and methodology for processor chips, including synthesis, place and route, and timing analysis, collaborating closely with design teams.
Top Skills: Eda ToolsPerlPythonTclVerilogVhdl
3 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Semiconductor
The Senior Staff Engineer in DFT will define DFT strategies, architect DFT solutions, mentor engineers, automate processes, and collaborate cross-functionally in ASIC/SoC programs.
Top Skills: AsicCadenceDftMentorPerlPythonShellSocSpyglass DftSynopsysTcl
3 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
6-6 Annually
Senior level
6-6 Annually
Senior level
Semiconductor
The Staff Engineer - DFT will develop DFT solutions, optimize test methodologies, collaborate with multiple teams, and validate designs for complex ASIC/SoC projects.
Top Skills: AsicCadenceDft ArchitectureDigital Circuit DesignMentorPerlPythonRtl DesignShellSocSynopsysTcl
3 Days AgoSaved
In-Office
2 Locations
Expert/Leader
Expert/Leader
Semiconductor
Lead DV execution for IP and SoC, improve DV processes, and collaborate with multiple teams on test plans and simulations.
Top Skills: C/C++PerlPythonShellSystemverilogUnix/LinuxUvmVerilog
Reposted 3 Days AgoSaved
In-Office
Bucharest, ROU
Mid level
Mid level
Semiconductor
You will work on physical design and methodology for high-performance processor chips, involving RTL code synthesis, timing analysis, and verification checks.
Top Skills: Cadence GenusCalibreFormalityInnovusLecPrimerailPrimetimeSynopsys Fusion CompilerSynopsys Ic CompilerTempusVoltus
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Reposted 3 Days AgoSaved
In-Office
2 Locations
Mid level
Mid level
Semiconductor
The Analog IC Design Staff Engineer will design high-speed and high-performance SerDes circuits, provide layout instructions, and work on IP validation with SoC teams.
Top Skills: AdeAnalog Ic DesignCad ToolsCmosMatlabSerdesSpectreSpiceVerilogVirtuoso
Reposted 3 Days AgoSaved
In-Office
2 Locations
Senior level
Senior level
Semiconductor
Design and implement firmware for embedded systems, ensuring performance and reliability. Collaborate with cross-functional teams, debug issues, mentor juniors, and adopt modern practices.
Top Skills: AnsibleCC++Ci/CdGitJenkinsPythonRust
3 Days AgoSaved
In-Office
Santa Clara, CA, USA
173K-260K Annually
Expert/Leader
173K-260K Annually
Expert/Leader
Semiconductor
Lead product marketing strategies for NSX Cloud & AI switching solutions. Drive competitive product roadmaps, collaborate with engineering and sales teams, and create market analysis for new product offerings.
Top Skills: EthernetPcieUalinkUec
3 Days AgoSaved
In-Office
Santa Clara, CA, USA
105K-158K Annually
Junior
105K-158K Annually
Junior
Semiconductor
The Staff Physical Design Engineer will perform synthesis, routing, and verification tasks, addressing design challenges in semiconductor solutions, collaborating with RTL design teams, and tackling timing and logic issues in complex logic blocks.
Top Skills: CadencePerlPythonSynopsysTcl
3 Days AgoSaved
In-Office
Santa Clara, CA, USA
105K-158K Annually
Mid level
105K-158K Annually
Mid level
Semiconductor
The role involves performing synthesis, place and route, and timing analysis on complex logic blocks, collaborating with design teams to address timing issues and improve designs in advanced semiconductor technologies.
Top Skills: CadenceFcInnovusPerlPythonSynopsysTcl
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