Top Tech Jobs & Startup Jobs

The Senior Staff Digital Design Engineer will design and integrate high-performance wireline PHY IPs, focusing on digital design, RTL implementation, and collaboration with mixed-signal teams to deliver robust SerDes solutions.

Design and optimize analog mixed-signal layouts (RX, TX, PLL); perform floorplanning, custom layout, and verification (DRC, LVS, ANT, LUP, ESD, EM/IR); collaborate with circuit designers, document methodologies, and mentor junior engineers to meet specifications and schedules.

The role involves leading digital block design from architecture to implementation, optimizing performance, and collaborating with verification engineers for alignment between design and verification goals.

The role involves developing verification environments, test plans, and tools for SoCs, collaborating with teams, and debugging failures.

Develop and draw analog/mixed-signal layouts for high-speed SerDes and other AMS IP in FinFET/deep-submicron processes. Collaborate with circuit designers and PV teams to resolve DRC/LVS/ANT/ERC/EMIR issues, using Cadence Virtuoso, Synopsys Custom Compiler, and Mentor Calibre. Provide feedback on schematics, support lab validation, and work across teams to achieve production-ready SoC layouts.

The role involves developing verification environments, writing test plans, debugging, and verifying SoC designs. It requires collaboration with designers and strong verification skills.

Manage and build a design team for SoC and complex sub-systems, develop methodologies for semiconductor processes, and provide technical mentoring while overseeing project timelines and progress metrics.

Responsible for customer technical leadership, resolving complex issues, product development feedback, and creating technical documentation. Collaborate cross-functionally and perform lab validation to support high-speed interface technologies.

Lead NPI for silicon photonics and co-packaged optical transceivers, driving manufacturing readiness, DfM, yield improvement, characterization, PFMEA, and volume production transfers while partnering with global cross-functional teams.

Lead micro‑architecture and RTL development for high‑performance connectivity ASICs. Define SoC specs, implement SystemVerilog RTL, drive front‑end flows (lint/CDC/synthesis/STA), support timing closure and PNR, collaborate on verification, pre‑ and post‑silicon validation, and mentor cross‑functional teams to deliver tape‑out ready designs.