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Manage end-to-end execution of Central CAD & Design Services programs: planning, schedules, risk tracking, stakeholder cadence, CAD/EDA readiness, communications, dashboards, JIRA/Confluence/SharePoint operations, and process improvements leveraging productivity and enterprise AI tools to scale program management.

Plan and conduct confidential, on-site one-on-one listening sessions; identify themes and hotspots; draft de-identified executive reports; escalate legal/compliance/safety issues; coordinate logistics; partner with HR, Legal, Compliance and leaders; continually improve session approach and reporting.

The Principal Engineer will lead digital IC design, focusing on complex SoCs, developing RTL, integrating IPs, and collaborating across teams while mentoring junior members.

The role involves creating functional models for SoC simulations, collaborating with software teams, and diagnosing firmware issues to enhance development efficiency.

As an Analog Layout Staff Engineer, you'll collaborate with global teams to design, simulate, and verify analog circuits, managing full development cycles and ensuring effective communication across diverse teams.

The Principal Engineer will lead the design and development of high-speed PAM/Coherent DSPs for Marvell, working on RTL coding, verification, and integration of IPs in collaboration with cross-functional teams.

The Analog Design Engineer, Principal will design circuits for high-speed optical transceivers, supervise layout activities, validate models, and mentor junior designers while collaborating across teams.

The Staff Application Engineer will test, debug, and analyze silicon-level applications, develop validation test plans, provide technical support, and interact with customers to ensure successful implementations of products.

The role involves designing, developing, and verifying digital ICs, focusing on RTL coding, DFT, and collaboration with cross-functional teams for high-speed DSP products.

Lead advanced packaging technology roadmap and development for high-performance AI/HPC and networking products. Define package architecture, chiplet topology, PDN and thermal strategies; run signal/power integrity and EM simulations; partner with silicon teams, OSATs and foundries; drive manufacturability, qualification, and volume readiness while creating IP and proof-of-concept technologies.