Senior Staff Digital Verification Engineer – Wireline PHYs

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

This is an existing vacancy.

Your Team, Your Impact

As a Design Verification Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Data Center, Storage, Security, and Networking.
You’ll be focusing on verification of wireline PHY IP for high-performance SoCs and ASICs. You will be responsible for developing comprehensive verification environments, test plans, and test suites to ensure the functionality, performance, and compliance of PHY designs with industry standards.

What You Can Expect

• Develop verification environments in UVM for IP blocks targeting SerDes and Parallel Optics applications.
• Define verification test plans with architecture and design teams, covering all requirements and corner cases.
• Collaborate with analog teams to understand and implement verification requirements for AMS simulations.
• Develop directed and constrained random functional verification tests to achieve comprehensive coverage of PHY functionality.
• Create checkers and scoreboards to verify correct operation across multiple speeds and data formats.
• Implement coverage models and drive verification to reach coverage targets, including code coverage, functional coverage, and assertion coverage.
• Debug test failures using waveform analysis tools and work with designers to resolve issues.
• Develop verification infrastructure including monitors, and drivers for various interfaces (APB, AHB, AXI).
• Write Python, Perl, or TCL scripts to automate verification tasks, improve efficiency, and analyze results.
• Collaborate with firmware teams to verify firmware-hardware interactions and microcontroller integration.
• Mentor junior verification engineers and contribute to improving verification methodologies and best practices.
• Maintain regression test suites and analyze verification metrics to ensure quality and tape-out readiness.

What We're Looking For

• BS/MS degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
• Strong experience with UVM and SystemVerilog for verification environment development.
• Hands-on experience with Verilog, SystemVerilog, and UVM for creating test benches, test plans, and verification environments.
• Experience with constrained random verification and coverage-driven verification methodologies.
• Familiarity with digital verification in Analog/Mixed-Signal (AMS) designs, preferably in the area of high-speed PHYs for wireline communications (e.g. SerDes, D2D, DDR).
• Some knowledge of the usage of analog behavioral models in the verification of AMS designs.
• Experience in the use of formal verification and/or assertion-based verification (ABV) would be useful
• Proficiency in scripting languages (Python, Perl, TCL) for test automation and verification infrastructure.
• Experience with protocol checkers, VIPs (Verification IPs), and industry-standard verification tools.
• Proven debugging skills and experience with waveform analysis and coverage analysis tools.
• Preferred: understanding of firmware-hardware interaction and system bring-up tools.

Expected Base Pay Range (CAD)

118,700 - 158,300, $ per annum

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement, and no hiring decisions are made solely on the basis of automated processing.

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