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Lead the architecture and execution of next-generation HBM PHY solutions, focusing on system requirements and driving design teams for optimal performance and scalability.

The Analog Layout Engineer will design and verify high-speed analog circuits using CAD tools, collaborating with global teams to ensure project specifications are met.

The engineer will design, verify, and evaluate digital circuits in high-speed ICs, improve design methodologies, and collaborate across teams for SerDes IP solutions.

The role involves architecting automated tools for DFT in custom chip design, improving project tracking, regression management, and mentoring teams on best practices.

As a Senior Analog Layout Engineer, you'll collaborate globally, running simulations and verifications using Cadence Virtuoso while owning the development lifecycle of analog circuit designs.

The role involves developing verification plans for high-speed memory interfaces, building verification environments, and collaborating with design teams for compliance and coverage closure in ASIC/SoC projects.

Lead micro-architecture definition, RTL implementation, and integration of DDR/LPDDR/HBM subsystems. Collaborate with architecture, verification, PD, DFT, firmware, and validation teams for sign-off and silicon bring-up. Drive design quality, coding best practices, debug performance/functional issues, and mentor junior designers.

Lead end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.x/4.0) subsystems using UVM/SystemVerilog. Develop verification plans, testbenches, constrained-random and directed tests, SVA checkers, and coverage-driven verification. Debug protocol-level issues, integrate VIP, run emulation/FPGA validation, automate regressions with scripting, and collaborate with design, firmware, and architecture teams to reach coverage closure and signoff.

Design, build, and validate complex SoC/subsystem emulation models and environments on Veloce/ZeBu/Palladium. Lead emulation bring-up, execute test plans, debug across RTL/firmware/toolchains, optimize performance, automate flows with scripting, and interface with EDA vendors to support verification, software readiness, and tape-out quality.

Lead PCIe/CXL subsystem micro-architecture, RTL design, integration, and sign-off. Collaborate with architecture, verification, physical design, firmware, and validation teams for silicon bring-up and post-silicon debug. Drive coding best practices, reuse, quality improvements, and mentor junior designers within the PCIe/CXL design domain.