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The role involves leading the design of Analog IC products, specifically CMOS transceiver/SERDES/PLL circuits. Responsibilities include architectural investigations, implementation, and design verification while managing delivery with a team of design engineers.

As a Senior Staff DFT Engineer at Marvell, you will implement DFT/Test on complex IP and SoCs for custom ASIC/SoC designs. You'll lead DFT/Test efforts, utilize DFT/Test architecture solutions, and develop methodologies for DFT/Test domains, leveraging your expertise in digital circuit design and verification using various EDA tools and scripting languages.

The Principal Physical Design Engineer will lead chip-level Place and Route activities ensuring high-performance designs. This role involves hands-on design work, technical leadership, tool optimization, and collaboration with various teams while mentoring junior engineers in the semiconductor field.

As a Senior Staff Engineer in Analog IC Design at Marvell, you will focus on high-speed and high-performance SerDes development. Responsibilities include designing mixed signal circuits, working with layout engineers, and collaborating with DSP and digital design teams on architecture development, characterization, and validation.

The Senior Staff Analog IC Design Engineer is responsible for designing complex CMOS transceiver/SERDES products, conducting detailed circuit design and verification using industry-standard tools, overseeing layout activities, and collaborating with cross-functional teams to ensure successful design integration and performance validation.

The Staff Engineer in Design Verification will analyze specifications to create test plans, develop UVM components, write test cases, run simulations, and debug issues. The role involves improving coverage results and proposing fixes through GLN/SDF simulation.

The role involves designing and verifying circuits such as PLL, DLL, ADC, and amplifiers, focusing on high-speed transceivers for communication infrastructure. The successful candidate will collaborate with layout and verification teams and manage the delivery of analog IP from concept to production.