Principal Engineer - Digital IC Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell’s high-speed DSPs are at the forefront of developing a PAM/Coherent ecosystem, providing low-power, high-performance solutions for cloud data center infrastructure, service providers, AI networks, enterprises, and 5G.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
You will be part of a highly-skilled, dynamic team driving the development of Marvell’s next-generation high-speed PAM/Coherent DSPs and PHY designs, which utilize cutting-edge CMOS technology.
As a member of a digital design team, you will be assisting in chip design working closely with architecture team, verification team, supporting back-end teams and timing closure.

What You Can Expect

• Define the sub system architecture, micro-architecture and register specifications for highly complex SoCs. Drive and participate in specification writeup
• working with the architecture team to understand the feature enhancement needs
• Develop overall efficient RTL using (System)Verilog, synthesis, and backend resources.
• Integrate internal and external vendor IPs.
• Design, debug, and support ICs, IPs and block DFT
• Ensuring all quality criteria is met.
• Work closely with the architecture, floorplanning, backend, verification, DFT, STA teams and other cross functional teams to produce high quality hardware.
• participate in various aspects of chip design RTL development, DFT design, synthesis, static timing analysis, formal equivalence, RTL lint, cross clock domain (CDC) analysis and functional verification.
• Work with the Verification team on pre-silicon verification tasks.
• Assist in design automation of various aspects of the CAD EDA flow.
• Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning
• Collaborate with cross-functional teams consisting of architects, designers, verification, physical design, and software/firmware engineers.
• Provide mentorship to the more junior team members

What We're Looking For

• Candidate must have a MS/PhDdegree in EE or related technical field(s) and 10 years of related professional experience.
• Fluent in RTL coding design techniques. Experience, DFT, resets, LEC, Lint, etc
• Experience working with multi-clock designs.
• Experience on synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience on Test structures for DFT, IP Integration, Fault models, coverage improvement techniques.
• Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up)
• Ability to multi-task and must be flexible and adaptable to a rapidly changing and demanding environment.
• Must be a team player with a strong can-do attitude.
• Effective communication and presentation skills.
• Design experience in high speed (>1 GHz)/high-performance DSP products is highly desirable.
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is highly desirable.

Expected Base Pay Range

64,500 - 86,000, EUR per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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