Top Tech Jobs & Startup Jobs

Design and verify high-speed digital ASIC blocks for optical Ethernet transceivers: RTL development, synthesis, STA, formal/CDC checks, integration of vendor IP, post-silicon debug, and CAD/EDA automation support from micro-architecture through timing closure and customer deployment.

Lead product marketing for Marvell Connectivity across APAC. Act as liaison between integrators, hyperscalers, and end customers; align supply and demand; drive business growth through customer relationships and sales collaboration; manage material, cost, ASP and gross margin reviews; coordinate cross-functional teams; travel and work off-hours with US teams.

Lead test engineering for NPI: define test plans, design ATE hardware, implement production and characterization test programs, perform silicon bring-up, and optimize test time and yield. Collaborate with product engineering, QA, program management, and operations using ATE platforms and test instruments.

Senior individual contributor owning IP release qualification for SoC subsystems: enforce RTL static quality (lint/CDC/RDC), validate synthesis readiness (SDC/UPF), ensure DFT/test readiness, manage IP delivery checklists and packaging, triage integration issues with SoC teams and vendors, and drive cross-functional alignment and automation to meet production-quality schedules.

Design and own core Python-based verification infrastructure: declarative build graph, run-record store, simulator backends, failure bundles, CI/grid integrations, and operational deployment; support AI agents with deterministic guardrails and provide docs and rollout support to DV teams.

Lead the SOC design team, manage high-quality SOC designs, integrate IPs, and ensure successful product execution through collaboration and technical leadership.

Design, implement, verify, and document micro-architecture and RTL for complex power-management ASICs. Own end-to-end development from architecture and RTL coding to synthesis, timing closure, formal and gate-level verification, silicon bring-up, documentation, and cross-functional reviews while improving design and verification methodologies.

Lead and define design verification strategy for semiconductor IP/SoC, develop and execute verification plans and testbenches, debug RTL and silicon issues, mentor engineers, and collaborate with cross-functional teams to ensure product quality and delivery.

Lead verification architecture, execution, emulation and post-silicon validation for next-generation ASICs. Drive verification methodologies, lab bring-up, emulation toward successful tapeout, and lead cross-functional ASIC development teams.

Lead and own end-to-end subsystem design verification: define DV processes, architect and implement UVM/C testbenches, develop and execute test plans, collaborate across IP/SoC teams, debug simulation failures, drive coverage closure and support post-silicon bring-up.