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Work as a Senior Staff Design Verification Engineer at Marvell, responsible for verifying circuitry in chips for high-speed data transfers. Requires 8+ years of experience in chip design verification, expertise in System Verilog, UVM, and DDR technologies. Strong communication and collaboration skills are essential.

ASIC design engineer responsible for the design, verification, and evaluation of digital circuits in high-speed data communication ICs. Focus on improving design verification methodology and flow, collaborating with analog and DSP teams, and providing support to product teams for both pre and post silicon.

Marvell Semiconductor is seeking a Sr. Staff Technical IP Project Manager to oversee the end-to-end process of IP development and SOC-IP integration support. Responsibilities include collaborating with cross-functional teams, providing expert guidance on IP selection, driving continuous improvement initiatives, and acting as a key point of contact for stakeholders. The ideal candidate will have a Bachelor's degree in Electrical Engineering, 8+ years of experience in semiconductor IP development, and proficiency in project management tools and methodologies. Strong leadership, communication, and interpersonal skills are required.

Develop test plans for verification based on architecture and design specifications. Write tests in various languages to test logical features in ASIC and SOC design blocks. Analyze coverage and conduct reviews of design and verification tasks.

Work as a Staff Design Verification Engineer at Marvell, responsible for verifying RTL engineers' designs, running simulations, debugging, and presenting test plans. Requires Bachelor's or Master's degree in Computer Science or Electrical Engineering with 3-5 years of experience.

Seeking an RF and Analog Design Engineer with 5+ years of experience in high-performance RF/Analog Receiver/TIA design. Responsibilities include designing high-speed broadband ICs, leading edge transimpedance amplifier design, developing transmission line structures, and collaborating on post-silicon validation and customer support.

Looking for a talented 3rd party IP integration engineer with a minimum of 7 years of experience in project management and ASIC design flows. Responsibilities include managing 3rd party developers, integrating DDR type interfaces, and collaborating with internal and external teams for successful core integration.