Top Tech Jobs & Startup Jobs

Supports semiconductor engineering labs through hardware and software installation, server and networking administration, PCB debugging and precision rework, board bring-up, validation, inventory management, and infrastructure troubleshooting. Performs soldering, BGA and SMT repairs, socket and connector replacement, rack mounting, cabling, diagnostic testing, and documentation. Requires independent work in data center environments, collaboration with hardware and validation teams, and occasional coordination with remote teams.

Leads DFT architecture, implementation, validation, timing analysis, pattern generation, and post-silicon bring-up for complex mixed-signal SoCs. Defines and improves DFT methodologies and tools across multiple chip generations, while mentoring and guiding a team of DFT engineers. Requires deep experience with SCAN, MBIST, IP-DFT, STA, DFX, ASIC design flows, and industry-standard Cadence, Mentor, and Synopsys tools.

Staff DFT Engineer responsible for implementing scan, compression, OCC, wrappers, and MBIST; running ATPG, DFT DRC, simulations, and coverage analysis; supporting timing closure and silicon bring-up; debugging ATE patterns; and automating DFT flows with scripts. The role requires collaboration with physical design and STA teams on advanced ASIC programs.

Define and implement DFT architecture for complex SoCs, including hierarchical DFT, scan, compression, ATPG, MBIST, JTAG, and at-speed testing. Lead DFT sign-off, timing and equivalence checks, silicon debug, failure diagnosis, yield learning, and handoff to physical design and ATE teams. Mentor engineers, coordinate cross-functionally, and improve DFT methodology and automation for advanced-node optical DSP products.

Leads complex semiconductor platform programs from concept through production readiness. Coordinates board, switching, optics, silicon, firmware, software, validation, manufacturing, supply chain, customers, and executive stakeholders. Owns integrated plans, technical integration, risk mitigation, validation, issue resolution, customer commitments, and production transition for hyperscale cloud and networking solutions. Improves program execution practices while balancing schedule, scope, quality, cost, resources, and platform objectives.

Owns technical development programs end to end, including design, cohort planning, training, mentoring, workshops, events, communications, evaluation, and continuous improvement. Partners with engineering teams and senior stakeholders to assess development needs, define objectives and metrics, manage milestones and risks, coordinate global delivery, and apply AI and analytics. Maintains program infrastructure, budgets, vendors, websites, and toolkits while supporting technical conferences and other development initiatives.

Leads the global strategy, governance, roadmap, budget, and delivery of technical training, career development, and technical leadership programs. Partners with senior engineering leaders, conducts skills and workforce analyses, designs scalable programs, and measures outcomes such as retention, productivity, and technical bench strength. Guides regional program managers, mentors team members, evaluates emerging technologies, and aligns technical development initiatives with engineering priorities and product roadmaps.

Leads semiconductor IP development and delivery from conception through mass production release. Manages dependencies, deliverables, specifications, milestones, risks, and cross-functional engineering teams across analog, logic, DFT, layout, timing, validation, and place-and-route functions. Chairs status meetings, communicates program updates to executive stakeholders, drives requirements closure, supports program management processes, and provides matrixed leadership to engineering managers.

Designs analog integrated circuit layouts from schematics using CAD tools and Cadence Virtuoso. Runs simulations and verification, debugs and refines layouts with analog IC designers, and collaborates with global engineering teams. Presents progress, communicates technical issues and solutions, and contributes to semiconductor projects from development through verification.

Owns analog and mixed-signal verification for broadband RF/TIA and high-speed communication ICs. Develops verification plans, test cases, coverage-focused testbenches, and simulations using industry-standard methodologies. Analyzes results, documents compliance, collaborates with circuit design and layout teams to resolve issues, and supports multiple CMOS and SiGe BiCMOS process nodes.