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Own demand forecasting, supply planning, and finished-goods inventory to meet S&OP objectives. Build and execute weekly, monthly, and quarterly demand-supply plans; monitor planned vs. actual builds and inventory across SKUs; translate forecasts into executable build plans with Manufacturing and Global Supply Management; lead scenario planning and risk mitigation under capacity or component constraints; and drive continuous improvement of planning processes, tools, and models.

The Quality Engineer will oversee quality assurance processes for suppliers and integrators of advanced AI hardware, ensuring compliance with standards and driving continuous improvement.

Manage corporate governance, board processes, financings, transaction closings, entity and equity administration, contract lifecycle tasks, and maintain legal records and workflows to support a rapidly scaling hardware and AI infrastructure company.

The DFT Engineer ensures efficient testability of ICs, develops DFT architectures, verifies implementations, and collaborates with teams for optimal production support.

Manage ASIC projects, coordinating between teams, managing vendor relationships, and ensuring timely delivery while communicating risks and project status to stakeholders.

Build and embed LLM-agent workflows into silicon engineering flows (RTL, verification, DFT, physical design, validation). Integrate agents with simulators, regressions, lab equipment, and CI; design rigorous evals, drive adoption, and accelerate chip development through measurable automation.

The Talent Intern will handle scheduling, logistics of interviews, manage candidate communications, support operational recruiting tasks, and improve the candidate experience while collaborating with recruitment teams.

Lead the full-cycle recruiting process for technical talent, partner with hiring managers, and enhance candidate experience in a high-paced environment.

Intern will develop firmware for ASICs, focusing on hardware reliability, performance, and collaboration with cross-functional teams to support AI applications.

As a Physical Design intern, you will assist in silicon design, improve iteration speed, develop design flows, and conduct final design checks.