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Responsibilities include contributing to verification methodology, creating testbenches for silicon validation, and driving reviews on verification progress.

The AI Runtime System Software Engineer will design and implement system software components, optimize ML workloads, and collaborate with hardware teams, requiring strong Linux and C programming experience.

The Bluespec Design Engineer will develop silicon designs using Bluespec and Haskell, focusing on performance and reusable libraries for hardware architecture.

As a Runtime Engineer, you will build and manage the host-side interface library, design custom-kernel ABI, and develop Python bindings while also improving LLM inference serving stacks. You'll collaborate on device memory management, runtime overhead, and performance targets.

Lead power architecture for server-class AI accelerators: define budgets, models, and estimation frameworks; correlate architecture to implementation; partner with architecture/RTL/PD/firmware/platform teams; surface cross-functional power tradeoffs; define power-control, throttling, and telemetry to guide implementation.

Design and deliver high-performance silicon subsystems from micro-architecture through sign-off. Own subsystem or chip-level RTL, collaborate with verification, DFT, and physical design teams, drive reviews, achieve area/timing closure, and ensure performance-power-area targets for ASIC/SoC products.

Lead power estimation, modeling, and analysis for AI accelerator SoCs. Perform RTL/gate/post-layout power analysis, build energy models, identify power-reduction opportunities across SoC subsystems, drive optimizations with architects and physical design teams, and develop automation and dashboards to accelerate analysis and sign-off.

Build infrastructure, tooling, and a Rust-based simulator; implement host-side interface libraries; write targeted and randomized tests to exercise corner cases; collaborate with hardware, architecture, and software teams to turn specifications into testable properties.

Drive verification from architecture/design to production silicon by developing scalable methodology, creating testbenches and portable tests, executing subsystem and full-chip verification, achieving coverage closure, and leading reviews toward sign-off, tapeout, and silicon bring-up.

Lead cross-functional execution for advanced SoC programs from planning through tapeout and production. Build playbooks, trackers, risk registers, and executive dashboards. Drive milestone governance, dependency management, technical risk mitigation, design reviews, pre-silicon validation, tapeout readiness, silicon bring-up, and executive communications across PD, validation, and external vendors.