Top Tech Jobs & Startup Jobs

The role involves coordinating test operations, managing relationships across product groups, executing test activities, and improving gross margins in semiconductor test manufacturing.

The Sr Test Operations Engineer oversees test manufacturing support, ensuring operational excellence and improving performance metrics in semiconductor manufacturing. Responsibilities include collaboration with global teams and management of test activities.

Design and implement DFT architecture for SoC/ASICs, including scan, scan compression, boundary scan, and MBIST. Develop hierarchical and low-power DFT, create scan ATPG and MBIST testbenches, run pre/post-layout simulations, perform test time and coverage analysis, and collaborate with test engineering for production test bring-up. RTL and timing/constraint expertise required.

Verify analog/mixed-signal ICs and systems by implementing IC/system-level test cases, developing event-driven models for analog components, running simulations and waveform analysis, automating execution and coverage collection, and collaborating with cross-functional teams.

Support end-to-end GaN tape-out execution including PCM layout, alignment mark and reticle mask layout, DRC and mask data verification, MEBES checks, mask ordering and vendor coordination, and cross-cultural communication with Japanese and global teams.

Lead definition and execution of AI/ML initiatives across semiconductor design flows, deploying agentic AI for frontend and backend EDA tasks. Build scalable data and model pipelines, integrate AI into engineering toolchains, measure ROI via KPIs, and grow a high-performance team while aligning with enterprise AI governance.

Lead post-silicon application, debug, and validation for Renesas memory interface products. Interface with cross-functional teams, support product lifecycle, develop test hardware/software, write application notes, and work with customers to optimize product performance.

Define and evaluate SoC architectures for low-power, compact, cost-effective connectivity ICs; derive IP blocks, assess feasibility, run performance simulations, produce specifications and test/verification plans, and track market and competitive trends.

Lead translation of customer and standards requirements into SoC architectures and target specifications. Define low-power, low-cost connectivity SoC architectures, derive new IP blocks, run feasibility and performance simulations, select external IP/vendors, and produce specification, verification, and test documentation. Monitor market/technology trends and perform competitive analysis.

Lead design-in and customer support for Renesas DC-DC and multiphase power solutions: perform schematic and PCB reviews, simulate and debug converters, author application notes, train FAEs, support on-site/remote customer engineering, and inform product definition through system-level analysis and market research.