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Design and lead development of high-performance O-RAN and 5G/6G software for an AI-RAN accelerator. Responsibilities include L1/L2 processing, real-time wireless pipelines, SDR and RF hardware integration, AI/ML applications, system testing, troubleshooting, documentation, and technical collaboration with operators and partners.

Supports Project Leaders with project coordination, schedule and task tracking, risk and issue management, stakeholder communication, meeting documentation, follow-up, reporting, and customer materials. Collaborates with hardware, software, architecture, business, overseas, and government-related teams. The role requires strong Japanese business writing, basic English communication, comfort with technical information, organization, accuracy, initiative, and adaptability in a fast-paced AI semiconductor environment.

Lead SoC RTL design, integration, implementation, and quality checks across frontend, DFT, verification, and physical design. Own PPA, constraints, clocking, boot, low-power architecture, interfaces, memory subsystems, and chip-level integration. Collaborate with global architecture and engineering teams, mentor engineers, evaluate IPs, support production-quality silicon, and influence technical strategy. The role requires leadership in SoC design and verification, advanced connectivity and processor architectures, and expertise in lint, CDC, RDC, power-aware design, chiplets, and die-to-die technologies.

Lead end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and IP blocks. Drive PPA optimization, synthesis, floorplanning, placement, CTS, routing, STA, power planning (UPF), timing closure and sign-off using Synopsys/Cadence tools. Define methodologies, collaborate cross-functionally, coordinate external implementation partners, and mentor junior engineers to ensure high-quality tape-outs and continuous process improvements.

This internship opportunity allows candidates to gain experience in an on-site environment, specifically at the Tokyo or India office, under a flexible schedule.

You will design, develop, and maintain software for Edge AI devices, leveraging robust debugging skills and collaborating on innovative technologies.

Manage ASIC program execution across schedule, performance, power, cost, and quality. Track risks, enforce change control, run milestone reviews, report to senior management, and coordinate cross-functional teams to ensure timely delivery of SOC products.

Collaborate with engineers to extend compiler/toolchain for high-performance ML model deployment on AI hardware. Requires significant software engineering experience and knowledge of ML.

You will develop and optimize machine learning models for EdgeCortix's hardware, collaborating with engineers to meet AI performance goals.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.