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The Senior Accountant will manage financial reporting, closing processes, budgeting, and audits, while building scalable accounting systems in a fast-paced startup environment.

This internship opportunity allows candidates to gain experience in an on-site environment, specifically at the Tokyo or India office, under a flexible schedule.

Lead end-to-end physical implementation (RTL-to-GDSII) of AI SoCs, chiplets, and IP blocks. Drive PPA optimization, synthesis, floorplanning, placement, CTS, routing, STA, power planning (UPF), timing closure and sign-off using Synopsys/Cadence tools. Define methodologies, collaborate cross-functionally, coordinate external implementation partners, and mentor junior engineers to ensure high-quality tape-outs and continuous process improvements.

You will design, develop, and maintain software for Edge AI devices, leveraging robust debugging skills and collaborating on innovative technologies.

Manage ASIC program execution across schedule, performance, power, cost, and quality. Track risks, enforce change control, run milestone reviews, report to senior management, and coordinate cross-functional teams to ensure timely delivery of SOC products.

Lead and execute the ASIC program to deliver SOCs on schedule, on budget, and to quality targets. Manage risks, dependencies, change control, milestones, metrics, and cross-functional coordination across design, verification, physical design, DFT, EDA partners, HW/SW, and validation. Report to senior management and ensure predictable execution.

Collaborate with engineers to extend compiler/toolchain for high-performance ML model deployment on AI hardware. Requires significant software engineering experience and knowledge of ML.

You will develop and optimize machine learning models for EdgeCortix's hardware, collaborating with engineers to meet AI performance goals.

As a Design Verification Engineer, you will verify AI hardware components, develop verification infrastructure, and automate testbench processes primarily using SystemVerilog/UVM.

Responsible for ASIC implementation tasks including synthesis, timing constraints, ECOs, validation, and supporting RTL development and physical design activities.