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Develop and maintain SystemVerilog/UVM verification environments for automotive connectivity SoCs. Create directed and constrained-random tests, integrate C DPI models, analyze coverage, execute regressions, debug RTL and firmware interactions, and verify processors, communication interfaces, mixed-signal subsystems, and E2B functionality. Support functional safety and ISO 26262 activities, automate workflows, document verification results, and collaborate with design, firmware, architecture, and validation teams.

Leads verification engineering teams developing automotive connectivity SoCs. Defines verification strategies, coverage goals, methodologies, infrastructure, and sign-off criteria for processor-based systems incorporating firmware, security, communications, memory, and mixed-signal components. Oversees E2B protocol verification, formal and assertion-based verification, debugging, safety analysis, ISO 26262 compliance, tapeout readiness, resource planning, and cross-functional collaboration. Requires hands-on expertise in SystemVerilog, UVM, DPI, SoC verification, and hardware-software co-verification, plus substantial people-management experience.

Develop and maintain SystemVerilog/UVM verification environments for automotive connectivity SoCs. Create directed and constrained-random tests, integrate C DPI models, analyze coverage, execute regressions, debug RTL and firmware interactions, and verify processors, communication interfaces, mixed-signal subsystems, safety mechanisms, and E2B functionality. Collaborate across design, architecture, firmware, validation, and functional safety teams while documenting verification plans, results, and closure activities.

Leads verification strategy and execution for automotive connectivity SoCs. Develops SystemVerilog/UVM environments, firmware-driven tests, C DPI models, protocol verification, coverage plans, and automation. Debugs RTL, software, and system-level issues; supports functional safety, fault injection, FPGA prototyping, silicon bring-up, and post-silicon validation. Collaborates across architecture, design, firmware, safety, and validation teams while mentoring engineers and driving verification closure.

Leads verification strategy and execution for automotive connectivity SoCs. Develops SystemVerilog/UVM environments, firmware-driven tests, C DPI models, coverage plans, and protocol verification. Debugs RTL, embedded software, and system-level issues; supports functional safety, fault injection, FPGA prototyping, silicon bring-up, and post-silicon validation. Collaborates cross-functionally, improves verification automation and methodology, mentors junior engineers, and drives verification closure.

Own block- and subsystem-level verification for hardware security IP and secure enclave designs. Develop SystemVerilog/UVM environments, test plans, checkers, scoreboards, assertions, coverage models, and constrained-random tests. Analyze regressions, debug RTL and simulation failures, verify processor-based systems and cryptographic accelerators, support emulation and post-silicon validation, improve reusable methodologies, and mentor junior engineers.

Supports strategic manufacturing and operational programs through PMO coordination, integrated scheduling, governance, readiness tracking, portfolio reporting, risk and dependency management, documentation, and cross-functional follow-up. The role consolidates project updates, monitors milestones and execution gaps, maintains RAID and action logs, prepares management-review materials, and supports escalation, mitigation, contingency planning, and project closure across operations, engineering, supply chain, IT, quality, and facilities.

Supports semiconductor manufacturing and product engineering through sustaining activities, yield and test-time improvements, material disposition, manufacturing control validation, product performance analysis, new product releases, and failure analysis. Collaborates with manufacturing and quality teams, analyzes data, addresses operational issues, and helps maintain product quality. The role requires strong communication, organization, independence, and willingness to work shifting schedules.

Develop embedded software, SDKs, application examples, proof-of-concept solutions, and host-side tools for ADI ASIC products. Participate in software design, testing, documentation, IDE integration, and full lifecycle development across Windows and Linux environments. Support debugging, board bring-up, device-driver integration, and customer adoption through maintainable code, test procedures, application notes, and user guides.

Serves as the senior SOC escalation point for complex cyber incidents, leading investigations, incident response, threat hunting, threat intelligence, detection engineering, and incident command. Mentors L1/L2 analysts, improves SOC playbooks and workflows, maps threats to MITRE ATT&CK, coordinates cross-functional response, supports compliance activities, and produces executive-ready assessments. The role also participates in global operations, vendor engagements, after-hours escalations, and continuous improvement initiatives.