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Provide technical leadership in mixed-signal IC design (ADCs, DACs, SerDes, PLLs) for SoC products using FinFET processes. Drive architecture decisions, transistor-level design, layout guidance, evaluation/test, mentorship, and cross-functional collaboration to deliver high-performance semiconductor solutions.

Maternity-cover Project Manager responsible for owning a portfolio of digital execution, product experience, and cross‑functional transformation initiatives. Ensure continuity of delivery, stakeholder alignment, and operational excellence across global teams while coordinating with Product Management, UX/design, IT, Analytics, and Business Unit partners.

Design, implement, and support cloud automation platforms and full-stack enterprise applications across AWS and Azure. Build frontend UIs, backend microservices/APIs, databases, CI/CD, and IaC. Integrate governance, security, identity, and cost/asset automation; collaborate with cross-functional teams and support production deployments and monitoring.

Design, implement, and maintain monitoring and observability infrastructure using Prometheus, Grafana, Nagios, SolarWinds and Kafka. Build KPI standards, AI-based anomaly detection, SLAs/SLOs, automation scripts (bash/Python/Go), runbooks, and collaborate with DevOps and application teams to optimize performance and reliability.

Design, build, and support cloud automation platforms and enterprise web applications across AWS/Azure (GCP preferred). Implement front-end React/TypeScript UIs, backend microservices/APIs, databases, CI/CD, IaC, and cloud automation workflows. Collaborate with cloud, security, FinOps, and platform teams to deliver secure, scalable self-service provisioning, governance, and operational automation. Own architecture through production support and mentor junior engineers.

Design and simulate transistor-level analog/mixed-signal IC blocks (amplifiers, converters, power circuits), define architectures, integrate blocks into mixed-signal systems, present results to teams/customers, support layout, lab evaluation and test, mentor others, and improve design methodologies to meet power, timing and functional objectives.

The Senior RFIC Design Engineer will design and evaluate RF integrated circuits, lead projects, and mentor junior engineers, focusing on RF Beamformers, up-down converters, and other RF products.

The Senior Principal Engineer will architect digital data paths for high-speed CMOS ICs, develop calibration algorithms, and lead design integration for broadband communication systems.

Lead architecture, transistor-level design, simulation and validation of power-management analog blocks (switching regulators, LDOs, charge pumps) for PMICs. Integrate blocks into mixed-signal SoCs, drive silicon bring-up and debug, present to customers, mentor engineers, and improve analog design methodologies to meet power, performance, and timing targets.

Lead and grow a global test engineering team for high-voltage/protection product development. Drive silicon validation, characterization, qualification, test development and manufacturing readiness. Partner cross-functionally with Design, Product, Reliability and Operations to resolve technical and manufacturing issues, improve yield and quality, manage project priorities and schedules, and champion automation and reusable test solutions while mentoring engineering talent.