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Lead development of test programs and ATE strategy for wafer-scale AI/ML accelerator chips. Design DFT and scalable wafer-level test methodologies, fault isolation, probe/load-board specs, characterization (di/dt, V-F), yield optimization, and cross-functional production debug.

The Kernel Optimization Engineer will develop high-performance software solutions by optimizing deep learning operations and designing new machine learning kernels for the Cerebras hardware system.

The Manufacturing Linux Network Engineer designs and maintains IT/network infrastructure across manufacturing facilities, ensuring high availability and security. They handle Linux server administration, network configuration, and collaborate with various teams for production systems connectivity.

Lead a team to improve the reliability of advanced compute clusters and manage failure analysis and debugging processes.

The Senior WAN Network Engineer will design, implement, and manage global WAN services, ensuring high performance and reliability, while collaborating with telecom providers and optimizing network protocols.

The Design Verification Engineer will develop and implement verification strategies, collaborate with teams, and enhance verification methodologies for silicon designs.

Lead a team of engineers to develop high-performance software solutions for AI and HPC workloads while mentoring team members and overseeing technical direction.

Join the SOTA Training Platform team to bring up ML models on Cerebras systems, enhancing performance across the software stack and debugging issues.

The role involves designing AI models and training methods leveraging wafer-scale hardware and collaborating with various teams and partners in AI and computational science.

Design and architect front-end network fabrics for AI/ML and HPC clusters. Automate deployment of network infrastructure, debug networking issues, and lead technical projects across teams.