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Master's thesis internship to design, simulate, and develop isolated gate driver IP for high-voltage power products. Work includes analog IC and power-electronics circuit design, behavioral modeling, and use of industry EDA tools under mentorship within the Milan Design Center. Six-month paid position focused on advancing IP efficiency and enabling next-generation semiconductor solutions.

Greet visitors and manage front desk operations, handle phone and email inquiries, manage mail and supplies, support calendar and travel logistics (SAP Concur), assist local/global teams and executives with scheduling, meeting setup, and administrative projects, and support HR and Facilities for events and outreach.

The Technology Layout Engineer will generate semiconductor layouts using Cadence software, manage mask releases, and support design enablement for semiconductor technology development.

The Memory Design Engineer will design and verify memory IPs, support silicon testing, and develop validation plans while collaborating with design teams on memory diagnostics.

The Lead, Development Product Engineering role involves coordinating testing and assembly processes, ensuring timely product release and optimizing operational workflows in semiconductor manufacturing.

Lead global product strategy and roadmap for Magnetic Current Sensing products. Drive product definition, NPI/IC development through Release-to-Market, collaborate with sales and engineering, engage lead customers for design-ins, and coordinate technical marketing, events, and cross-functional initiatives to grow market share in high-voltage power conversion and motor drive applications.

Manage HR communications and internal channels, run engagement campaigns and events, support employee relations and talent management, and build/maintain HR data dashboards ensuring data integrity and compliance.