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Develops and tests digital signal processing algorithms for fiber-optic communication systems and semiconductor products. Implements algorithm models in C, C++, and MATLAB, collaborates with hardware, software, and architecture teams, and contributes to systems-on-chip definition. Provides technical leadership in transmission technology, channel coding, system architecture, and partitioning.

Leads end-to-end IC substrate and package layout for complex SoCs and multi-die products, including bump planning, pin assignment, floorplanning, routing, stackup definition, SI/PI optimization, verification, signoff, and manufacturing release. Collaborates with physical design, assembly, reliability, manufacturing, OSAT, and substrate vendors. Designs advanced package architectures and supports tape-out while balancing performance, manufacturability, reliability, and cost. May automate workflows and mentor junior designers.

Leads optical hardware systems applications engineering, including team hiring and mentoring, customer design-in support, technical debugging, product testing, reference designs, documentation, vendor and lab management, and product roadmap support. Partners with sales, FAEs, marketing, and engineering teams to secure design wins, resolve customer issues, validate products, and improve reliability. Requires extensive optical transceiver, analog, RF, high-speed digital, PCB, and hardware/software debugging experience, with up to 30% travel.

Develop, maintain, debug, test, and qualify SoC design methodologies and EDA flows from RTL through GDS. Implement scripting-based workflows, verify flow signoff results, establish tool regressions, and integrate flows with engineering compute infrastructure. Support design engineers by resolving setup issues, documenting methodologies, training teams, and collaborating with IT and database management groups.

Provides technical leadership and architecture for IP, subsystem, and SoC verification. Owns verification strategies, UVM environments, coverage, regression, debug, failure triage, and sign-off. Drives AI-assisted and data-driven automation, partners with design and product teams, and mentors verification engineers. Requires deep ASIC verification expertise, leadership across complex programs, proficiency in SystemVerilog, UVM, Verilog, C/C++, scripting, Linux/Unix, and high-speed protocols.

Develop and validate analog serial transceiver ICs from specifications through production release. Design blocks including op-amps, comparators, references, bandgaps, charge pumps, high-voltage transmitters and receivers, and capless LDOs. Collaborate on layout, integration, design reviews, verification, reliability, yield, post-silicon debugging, system characterization, and productization support.

Leads ASIC design verification across IP, subsystem, and SoC levels. Defines test plans, develops reusable UVM environments, drives functional and code coverage closure, debugs complex issues, and owns verification deliverables through sign-off. Applies AI-assisted workflows to improve test generation, debug, coverage analysis, and regression efficiency. Collaborates with architecture, design, validation, and cross-functional teams while advancing verification automation, quality, and process improvements.

Develop RTL designs for ASIC and FPGA implementations, contribute to architecture and microarchitecture, perform block integration and debug, and support verification, synthesis, timing analysis, and design sign-off. Collaborate across engineering teams, document interfaces, support silicon bring-up and root-cause analysis, evaluate reusable IP, and implement low-power techniques such as clock gating and power optimization.

Develop and test embedded C software for DOCSIS home gateway SDKs in real-time operating systems. Collaborate with architecture and silicon teams, build user-space and kernel modules on ARM and ATOM processors, and solve system-wide issues spanning hardware interfaces, operating systems, networking, and applications. The role also involves using AI-driven development tools, mentoring engineers, and planning and leading projects.

Architects and leads digital verification strategies for complex analog mixed-signal ASIC products. Builds block, cluster, and full-chip UVM environments using constrained-random techniques; develops scoreboards, agents, sequencers, and monitors; debugs RTL and gate simulations; converts tests into ATE patterns; and collaborates with design, system, and test engineering teams to ensure first-silicon success.