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Lead architecture, design, simulation, and validation of high-speed precision CMOS ATE analog circuits. Own blocks through layout, verification, and post-layout analysis. Drive mixed-signal simulation strategy, mentor engineers, and collaborate with test, applications, and manufacturing to deliver robust silicon.

Lead analog architecture for ATE ICs, mentor engineers, drive innovations in circuit techniques, oversee design processes, and collaborate with stakeholders to achieve technical excellence.

The Staff Analog IC Layout Engineer will lead the physical layout of complex analog and mixed-signal integrated circuits, ensuring optimal design and verification while collaborating with various engineering teams.

Lead NPI from first silicon to high-volume manufacturing for precision analog and mixed-signal ICs. Develop and optimize wafer sort and final test solutions (Teradyne UltraFlex IGXL), correlate bench and ATE results, establish production limits, design/validate test hardware (load boards, probe cards, sockets), perform silicon debug/root-cause analysis, support qualification and transfer to OSAT, and create automation tools using Python and JMP to improve throughput and quality.

Design, simulate, and optimize high‑speed, precision CMOS analog circuits for ATE products. Perform layout, verification, and post‑layout simulation (Monte Carlo, SOAC, corners). Support mixed‑signal channel/chip simulation, IC characterization, test development, and qualification while collaborating with digital, layout, test, and applications teams.

Provide inside sales support to sell Elevate Semiconductor products, manage accounts, prepare proposals and forecasts, maintain CRM data, collaborate cross-functionally, and support revenue growth. Onsite in San Diego.

Lead the design and development of high-voltage analog circuits for ATE instrumentation, driving innovation from concept to production with a focus on precision and performance.