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Lead verification of cache and memory-subsystem functionality focused on coherency, ordering, correctness, and integration. Create verification strategies and test plans; develop testbenches, checkers, assertions, stimulus, and coverage; run directed and constrained-random tests; debug failures and drive fixes across RTL and infrastructure; collaborate with architecture and design teams; and improve methodology, automation, and team-wide verification quality.

Lead verification planning and execution for L2/L3 caches and cache-subsystem integration. Build and maintain SystemVerilog/UVM testbenches, checkers, assertions, scoreboards, constrained-random tests, and coverage models. Debug complex RTL/testbench issues, drive fixes, collaborate with architecture and design teams, close coverage holes, and contribute reusable methodology and automation to improve team verification quality and scalability.

Drive physical implementation and timing closure for high-performance chip designs. Architect advanced clock distribution and global interconnects, optimize RC/jitter/IR issues, collaborate with RTL/architecture teams, mentor engineers, and sign off on implementation using industry EDA tools.

Develop and maintain a scalable Verification Platform including VIPs, AIPs, and testbench components. Architect libraries in Scala/Chisel, build SystemVerilog/UVM VIPs, create test plans and testbenches, and educate DV teams on best practices.

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

Lead end-to-end physical design (synthesis, floorplan, P&R, signoff) for complex IPs, co-optimize RTL and microarchitecture to meet aggressive PPA targets, solve timing/routing/IR issues, apply advanced techniques across product classes, and mentor junior engineers.

Develop and maintain a modular build flow for Synopsys ZeBu and FPGA platforms, perform root-cause failure analysis across RISC-V hardware and software, use ZeBu/ILA/JTAG debugging features, automate debug workflows with Python/Bash, and collaborate with software and validation teams to integrate ZeBu runtime into SiFives internal build ecosystem.

Design, develop, upstream and release system software (Linux kernel, device drivers, OpenSBI, U-Boot, Yocto). Collaborate with architecture and hardware teams to integrate hardware features, debug complex multicore systems, and support device interfaces like PCIe, Ethernet, and CXL.

Develop and maintain a scalable Verification Platform: extend Chisel/CIRCT, build Scala libraries and Python tools for test harnesses, stimulus, and metadata querying, support end-to-end verification flows, and educate DV teams on best practices.

Own release readiness and delivery of SiFive IP customer drops; manage integration/configuration issues across Core/UnCore; generate release collateral and perform quality checks; drive schedule and risk tracking; collaborate with sales/support; debug cross-functionally and improve release automation.