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Own release readiness and delivery of SiFive IP customer drops; manage integration/configuration issues across Core/UnCore; generate release collateral and perform quality checks; drive schedule and risk tracking; collaborate with sales/support; debug cross-functionally and improve release automation.

Join SiFive to optimize and deploy AI models on RISC-V architectures, focusing on heterogeneous computing, inference stack integration, and kernel/compiler synergy.

The role involves verifying cache and memory-subsystem functionality, developing verification environments, analyzing failures, and collaborating with design teams.

Ownership of AWS EKS infrastructure and CI/CD pipelines (Terraform, GitHub Actions, Concourse, Jenkins). Implement observability, automation with Python, and maintain Docker/Helm deployments. Secondary focus on building scalable Django/Python backend APIs, PostgreSQL optimization, and integrating AWS services (SQS, S3, Lambda).

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Lead CPU subsystem verification by defining strategy, building UVM/SystemVerilog testbenches, creating constrained-random and assembly tests, debugging RTL/SOC issues, and mentoring junior engineers.

Lead physical implementation of high-frequency CPU core blocks from RTL to GDSII. Drive synthesis, place-and-route, timing closure, CTS, and signoff. Collaborate with architecture, RTL, and power teams for aggressive PPA optimization, improve physical design flows and automation, and solve core-specific datapath and congestion challenges.

Lead verification for a scalable cache-coherent interconnect subsystem: define strategy and test plans, build verification environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, create constrained-random and directed tests, debug across RTL/formal/software, and drive methodology and mentorship to improve verification quality and closure.

Lead verification for a scalable cache-coherent interconnect subsystem. Define strategy, develop environments, checkers, assertions and coverage, verify CHI/ACE/CXL/AXI flows, debug root causes, partner with architecture/RTL/formal teams, and mentor engineers to improve verification quality and signoff.

As a Senior Product Manager, you will articulate SiFive's product portfolio, collaborate with IP architects, and guide Sales during customer engagements. A strong background in product management within the semiconductor industry is required, along with technical marketing and customer interaction experience.