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Lead the Low Power Verification and Formal Equivalence methodologies, ensuring robust power intent and logical equivalence throughout RTL-to-GDSII flow.

Design and implement CPU microarchitecture features and ISA extensions using Chisel; integrate into Chisel/FIRRTL framework; perform sandbox verification and collaborate with verification, physical implementation, and performance teams to meet frequency, area, power, and performance goals. Produce documentation and participate in collaborative design.

Analyze and benchmark SiFive IP power consumption, correlate power models with RTL and silicon, work with architects and designers to optimize power/performance trade-offs, and innovate improvements to power analysis flows.

Lead a performance engineering team to research, model, and develop high-performance core architectures and microarchitectures. Design experiments, identify HW/SW bottlenecks, and work with design teams to implement and deliver performance targets in RTL and FPGA flows.

Research, model, and develop microarchitecture features for high-performance RISC-V processors. Design and run experiments, identify HW/SW performance bottlenecks, perform workload characterization and reduction, and collaborate with design teams to implement and deliver performance targets in RTL and FPGA prototypes.

Lead a performance engineering team to research, model, and develop high-performance CPU core architectures. Design experiments, analyze HW/SW performance bottlenecks, and work with design teams to implement and deliver RTL targets.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, develop robust UVM/SystemVerilog environments, write checkers/assertions, drive coverage closure, debug complex microarchitectural issues, and partner with architecture, RTL, performance, and software teams to raise verification quality and provide reusable methodology.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, build testbenches, assertions, and coverage models, perform root-cause debug, work with architecture/RTL/performance teams, and drive verification closure and reusable methodology across core generations.

Lead functional verification for high-performance out-of-order CPU cores. Plan and execute block-to-core verification, develop UVM/SystemVerilog testbenches, write coverage and assertions, create constrained-random and directed tests, debug failures, collaborate with architects and RTL teams, and contribute reusable DV methodology and infrastructure to achieve signoff-quality verification.

Lead verification planning and execution for high-performance out-of-order CPU core blocks (frontend, midcore, LSU, prefetch). Define verification strategies, develop environments, assertions, scoreboards, stimulus and coverage models, perform root-cause debug, partner with architecture and design teams, and deliver reusable methodology to close microarchitectural risks and achieve signoff.