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As a Principal Field Application Engineer at SiFive, you will lead pre-sales technical engagements with customers, focusing on CPU, SoC Architecture, Security, and Software/Firmware requirements. Responsibilities include customer demos, benchmarks, and proposing solutions. Ideal candidates have a strong background in CPU microarchitecture and SoC implementation.
As a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. Responsibilities include designing new features, performance improvements, and ISA extensions, collaborating with various teams for verification and optimization, and contributing to microarchitecture development and specification. Requirements include a BS/MS degree in computer science or related field, 3+ years of design experience, and proficiency in hardware design and software engineering skills.
SiFive is looking for an experienced System Software Engineer to work on designing and evaluating systems, writing software for Linux kernel, device drivers, OpenSBI, u-boot, and Yocto/OpenEmbedded. This role involves collaborating with hardware and software teams to create innovative solutions based on the RISC-V instruction set architecture.
Principal Architect role at SiFive focusing on creating scalable chip architectures and designing SoC for Performance Series products. Responsible for integrating components, developing multicore platforms, and trailblazing EDA tools. Requires expertise in RISC-V, Linux, and chip design.
Contribute to developing a Functional Safety and RAS solution portfolio for SiFive's IP Portfolio, collaborate with engineering and product teams, and support customers in identifying product requirements. Requires 5+ years of experience in IP developing with a Master's or PhD in a related technical field.
The architect role focused on debug, trace, and profiling to drive innovation in architecture, design, tool, and methods at SiFive.
Lead a team of engineers in power convergence, reduction, and modeling for high-performance cores. Responsible for power simulation, ASIC power analysis, and optimizing power impact at different levels. Must have strong organizational and communication skills to present power status to various teams. Experience with out of order core uArch and scripting in Python, Perl, or Tcl is required.
The Verification Engineer at SiFive will ensure the fidelity of new highly configurable cores and other related IPs by adopting state-of-the-art verification methodologies. They will create test plans, execute tests, and ensure verification quality through coverage metrics. This role offers the opportunity to work with cutting-edge technologies in CPU design.
SiFive is looking for a staff level hardware engineer passionate about designing industry-leading CPU and interconnect IP, focusing on RISC-V architecture. Responsibilities include enhancing existing IP, developing new IP, and working in a fast-paced environment to bring new hardware IP to market quickly with high quality.
As a Staff Formal Verification Engineer at SiFive, you will be responsible for identifying blocks for Formal Verification, creating test-plans, implementing and maintaining verification environments, applying FV techniques, debugging RTL, guiding team members, automating verification processes, reviewing setups with teams, and extending assertion libraries.
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