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The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

The Senior Design Verification Engineer will ensure functional correctness of SoCs/IPs, focusing on verification plans, environment development, debugging, coverage closure, and mentoring junior engineers.

The role involves developing verification strategies for high-performance silicon, focusing on both Formal Verification and UVM Simulation. Responsibilities include building robust verification environments, root-causing RTL bugs, and achieving complete coverage closure.

Design and develop system software including Linux kernel and drivers, collaborate with hardware teams, and debug complex systems for RISC-V processors.

The Staff Software Toolchain Engineer will enhance RISC-V extensions, optimize compilers, and integrate GNU toolchain recipes within a Linux system. Collaboration and high-quality toolchain product delivery are key responsibilities.

As a CPU Design Intern, you will develop RTL for RISC-V cores, gain knowledge in computer architecture, and work on performance and power optimization.

The role involves verifying cache and memory-subsystem functionality, developing verification environments, analyzing failures, and collaborating with design teams.

Join SiFive to optimize and deploy AI models on RISC-V architectures, focusing on heterogeneous computing, inference stack integration, and kernel/compiler synergy.

The Staff SDET will lead the architecture for automated testing infrastructure, mentor team members, and collaborate with cross-functional teams to ensure system quality in RISC-V embedded products.