As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
About the Role
We are seeking a highly skilled Staff Engineer to lead our Low Power Verification and Formal Equivalence signoff methodologies. In this critical role, you will be the ultimate owner of the static low power checks and formal verification flows for our advanced, high-performance designs. You will partner closely with Physical Design and Power teams to ensure robust power intent implementation and flawless logical equivalence throughout the RTL-to-GDSII flow, including managing complex, late-stage engineering changes.
Key Responsibilities
Low Power Signoff Ownership: Take full ownership of all static low power verification checks across the design hierarchy, ensuring complete coverage and zero low-power structural bugs.
UPF Strategy & Automation: Collaborate closely with Platform Engineering and Power architecture teams to architect, optimize, and automate Unified Power Format (UPF) coding and deployment.
Formal Equivalence Leadership: Own and drive the complete Formal Equivalence Checking flow, acting as the primary authority for ensuring logical equivalence from RTL through post-route, including managing complex Engineering Change Order (ECO) implementations.
Cross-Functional Optimization: Leverage your understanding of Physical Design limitations and power architectures to provide highly optimal, implementable UPF and equivalence solutions.
Required Qualifications
Education & Experience: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 7+ years of relevant industry experience in ASIC/SoC design and verification.
Power Intent Mastery: Deep, authoritative understanding of architecting and coding power intent using the Unified Power Format (UPF).
Static Power Verification: Proven expertise running, analyzing, and debugging static low power checks on both RTL and post-PNR netlists using industry-standard tools (e.g., Synopsys VC Low Power / VCLP).
Formal Signoff: Extensive, hands-on experience with Logical Equivalence Checking (LEC) and Formal Equivalence tools (e.g., Synopsys Formality), with specific expertise in driving formal ECO flows.
Low Power Libraries: Strong technical understanding of Power Management library cells and their physical/logical implications, including Isolation cells (ISO), Level Shifters (LS), Always-On (AON) cells, and Retention registers.
Preferred Qualifications
Physical Design Foundation: Solid foundational knowledge of the backend Physical Design (PD) flow, enabling you to anticipate implementation challenges and bridge the gap between frontend intent and backend realization.
Scripting & Automation: Strong scripting proficiency (TCL, Python, or Perl) to drive flow automation, custom rule creation, and methodology improvements.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 7+ years of relevant industry experience in ASIC/SoC design and verification
- Deep understanding of architecting and coding power intent using Unified Power Format (UPF)
- Experience running, analyzing, and debugging static low power checks using industry-standard tools
- Experience with Logical Equivalence Checking (LEC) and Formal Equivalence tools
- Understanding of Power Management library cells and their implications
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
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