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Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.

Lead sub-system level verification of high-speed IOs (PCIe/CXL) including test plan creation, SystemVerilog/Verilog/UVM testbench and test development, simulation and emulation, performance and interoperability verification, debugging failures, improving verification methodology, and mentoring junior engineers while collaborating with architects, RTL designers, and cross-functional teams.

Develop and execute verification plans and testbenches (UVM/SystemVerilog/C) for Security IP and embedded processor subsystems. Verify cryptography, secure boot, key management, and multi-clock/multi-power domain IP; debug failures, improve verification methodology, and mentor teammates toward product sign-off.

Lead end-to-end delivery of an Arm AGI SoC program from pre-silicon through commercialization. Maintain integrated program plans, drive cross-functional decisions, report status to senior leaders, align engineering/product/operations, identify risks and execute recovery plans, and ensure firmware, software, validation, and customer readiness for deployment.

Design and productize Hardware Security IP and subsystems for SoCs. Develop architectures, RTL, constraints; drive verification, debug, optimization, and sign-off. Mentor teammates and contribute to roadmaps, processes, and cross-team collaboration.

Lead full-cycle recruitment for technical and non-technical roles in Austin, partnering with hiring managers to build pipelines, source passive and active candidates, influence hiring decisions, and deliver inclusive candidate experiences. Drive employer branding, data-driven reporting, market insights, and offer strategy to meet hiring goals and support growth.

The role involves managing safety and cybersecurity for automotive SoC programs, ensuring compliance with standards, and improving development processes.

As a Staff Signal and Power Integrity Engineer, you will develop and analyze System-in-Package designs, enhance Arm IP performance, and lead technical oversight for related projects.

The Architect will improve Arm's hardware acceleration infrastructure through benchmarking, scheduling optimization, vendor API integration, and performance visualization, enhancing overall productivity.