Top Tech Jobs & Startup Jobs

Lead design and implement a scalable chassis automation tool that translates SoC architecture requirements into generated RTL, registers, verification collateral, and integration artifacts. Collaborate with architecture, RTL, verification, and integration teams, enable PPA analysis, integrate with front-end/back-end flows, and mentor junior engineers to deliver high-quality automated outputs.

Define end-to-end CPU architecture and microarchitecture features, set performance/power/area targets, model and analyze CPU performance and power, develop tests and simulations, specify new instructions, and collaborate with design, verification, and validation teams to deliver optimized CPU designs across product segments.

Lead supplier development and qualification for advanced substrate and wafer assembly technologies. Drive technical enablement across process steps (embedding, drilling, plating, lithography, metrology, electrical testing), manage readiness milestones, implement factory validation and yield-improvement plans, create micro schedules for new factory startups, and monitor ramp indicators to ensure incident-free production ramp and capacity introduction.

Lead end-to-end verification for chassis and interconnect IPs, build scalable UVM/SystemVerilog testbenches, drive simulation/formal convergence and coverage closure, collaborate with architecture/design/software, mentor engineers, and ensure functional signoff and performance/power goals.

Develop and integrate front-end semiconductor process flows, coordinate across fab disciplines, analyze yield and defects, perform root-cause and statistical analysis, optimize device performance, implement process control, and support technology transfer to high-volume manufacturing.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Lead process integration and yield activities in defect metrology: perform statistical and data mining analyses, drive low-yield investigations, design and run experiments (DOE), develop process flows and equipment configurations, conduct risk and reliability assessments, lead defect/metrology measurement in startup and high-volume manufacturing, mentor team members, and align technical strategy to improve yield and quality.

Perform RTL-to-GDS physical implementation for CPU blocks: synthesis, floorplanning, place-and-route, clock tree synthesis, STA, power/clock distribution, reliability, and noise analysis. Lead verification and signoff (formal equivalence, DRC/LVS, power integrity). Collaborate with logic, circuit, architecture, EDA vendors, and automation teams to optimize power, frequency, and area and improve physical design methodologies and flows.

The role involves leading wet etch and cleans development, focusing on advanced logic process integration and mentoring engineers.

Develop and optimize RF and analog test solutions from feasibility through production. Design test boards, perform ATE and bench characterization, debug functionality and performance, correlate ATE-to-DV, tune thermal and power recipes, and develop software to drive advanced test equipment to ensure product quality and yield.