Top Tech Jobs & Startup Jobs

Lead architecture and development of embedded firmware for high-speed coherent optical transceivers. Design system software, develop algorithms and low-level drivers, perform RTOS debug, system bring-up, and cross-functional coordination with ASIC, DSP, hardware, product, and quality teams. Interface with customers on SW architecture and support product transition to manufacturing.

Lead full-chip physical design: floorplanning, partitioning, clock and power planning, place-and-route, STA, power integrity, signoff, tool/flow improvements, collaboration across RTL, DFT, EDA vendors, foundry and post-silicon teams, and apply AI tools to improve productivity.

Design, develop, and maintain large-scale test automation for coherent optical transceivers; execute tests on product releases; collaborate with developers to resolve defects; document test results and publish software release notes to ensure hardware and software specifications are met.

Lead architecture and development of embedded firmware for coherent optical transceivers. Design algorithms and low-level C/C++ code for RTOS and bare-metal CPUs, drive cross-functional requirements with hardware, ASIC, DSP, and optics teams, participate in system bring-up, debugging, manufacturing transition, and customer technical discussions.

Drive customer success with Cilium Enterprise by designing and guiding production rollouts, building technical customer relationships, delivering workshops and training, collaborating with engineering/support, creating reference architectures and docs, and applying deep Kubernetes, cloud-native, networking, and observability expertise.

Lead bring-up, verification, calibration, and production-test optimization of coherent optical transceivers. Collaborate with DSP, software, hardware, and PIC teams to maximize performance, minimize power and size, and improve manufacturing yield and test automation.

Lead product management for Acacia client optics, driving requirements, roadmaps, lifecycle, manufacturability, supply chain, go-to-market, and cross-functional engineering and operations collaboration to deliver high-speed optical interconnect products.

Lead ASIC physical design for fullchip RTL-to-GDSII implementation: floorplanning, partitioning, clock/power planning, place-and-route, timing and power signoff, verification, and methodology improvements while collaborating with RTL, DFT, EDA vendors, foundry and post-silicon teams.

Lead RTL-to-GDSII physical implementation and methodology improvements, covering synthesis, floorplanning, P&R, CTS, STA, power integrity, sign-off flows, ECOs, and EDA tool/flow evaluation and automation across advanced process nodes.

Serve as Cisco Capital's strategic financial advisor for Global Enterprise accounts: structure complex financing deals, lead executive engagements, coordinate billing and operations, influence cross-functional teams, and exceed attachment financing revenue targets.