Top Tech Jobs & Startup Jobs

Lead ASIC STA/DFT efforts developing and validating timing constraints (block to full-chip) across implementation and post-silicon phases. Perform SDC validation, CDC checks, timing closure for DFT modes, create STA methodologies, and collaborate with cross-functional teams to resolve design and flow issues.

Lead evaluation, design, and qualification of high-speed interconnects and connectors from concept to production. Drive cross-functional supplier partnerships, mentor junior engineers, ensure signal integrity, mechanical reliability, manufacturability, and regulatory compliance, and deliver robust, cost-effective connectivity solutions for networking products.

Build and operate an internal AI platform enabling engineers to create, deploy, and run AI agents at scale. Design services, frameworks, and tooling for secure, reliable AI workflows; build automation and high-impact agents to improve developer productivity; partner across teams to deliver platform capabilities and establish best practices for testing, deployment, observability, and operational ownership.

Design-for-Test (DFT) engineer responsible for implementing DFT features, developing DFT IP, integrating test logic with RTL and physical design teams, enabling ATPG/ATE flows, and performing post-silicon validation and debug.

Lead design, deployment, and maintenance of large-scale Generative AI solutions (RAG and Agentic AI). Architect secure document processing pipelines, integrate responsible AI practices (toxicity/bias screening), implement data security and compliance, monitor AI infrastructure, and collaborate with cross-functional governance and legal teams.

Lead system-level hardware design for accelerated compute/server products from concept to production. Solve high-speed signal integrity and power distribution challenges, coordinate cross-functional teams and suppliers, manage JDMs, and deliver shipping products while enabling integration with software, mechanical, and SI disciplines.

Lead ASIC STA methodology, architecture, and verification for advanced-node chips. Define timing constraints, drive timing closure and ECOs, oversee parasitic extraction and OCV methodologies, mentor teams, create standards, and collaborate with packaging, hardware, and vendor partners to meet power, performance, and area goals.

Lead design and implementation of high-performance data plane software for DPU-based Smart Switches. Write and optimize C/C++ on Linux, build packet-processing and networking features, troubleshoot complex networking and customer issues, participate in architecture and code reviews, and mentor engineering teams to deliver scalable, reliable systems.

Lead and develop a solutions engineering team to design, demo, and deliver AI/ML solutions (LLMs, RAG, embeddings). Oversee pre-sales discovery, POCs, customer enablement, technical strategy, cross-functional alignment, escalation handling, hiring, and team enablement to drive revenue and customer success.

Lead and manage a team of AI hyperspecialist sales architects to influence enterprise AI purchasing, drive multi-year sales growth and portfolio profitability, coordinate cross-functional teams and partners, build C-level relationships, streamline sales strategy and execution, and deliver recurring revenue and renewal targets across global accounts.