Top Tech Jobs & Startup Jobs

Develop and maintain ASIC design verification environments. Build testbenches, write test plans and testcases, debug regressions, implement functional and code coverage, and verify complex SoC blocks using simulation, emulation, and AI-assisted methods to drive verification closure.

Design and validate high-speed hardware for Cisco 8000 series routers, driving product lifecycle from architecture through manufacturing. Responsibilities include board design using Cadence/Allegro/Concept, layout guidance, lab bring-up, debug with analyzers/oscilloscopes, writing specs and test plans, and cross-functional collaboration with ASIC, software, mechanical, manufacturing, and signal integrity teams.

Lead CDC/RDC methodology for ASIC subsystems: design and implement CDC-aware RTL, define CDC check flows and SDC constraints, perform static glitch and gate-level analysis, review/approve constraints and waivers, and collaborate with CAD to productionize robust, reusable silicon designs.

Lead full-chip physical design: floorplanning, partitioning, clock and power planning, place-and-route, STA, power integrity, signoff, tool/flow improvements, collaboration across RTL, DFT, EDA vendors, foundry and post-silicon teams, and apply AI tools to improve productivity.

Design and verify high-performance, multi-layer PCBs for next-generation networking hardware. Lead full board lifecycle: schematic/layout, high-speed signal and power integrity debugging, failure analysis, test-plan development, and design reviews to ensure product reliability.

Lead mechanical engineering design for Cisco routing products: drive specifications and standards, oversee DFM/BoM, supplier selection, prototyping, testing, failure analysis, and thermal/mechanical validation. Mentor junior engineers and coordinate cross-functional stakeholders to deliver manufacturable, cost-effective hardware.

Lead and grow a high-performing software sales team for Splunk/Cisco in the SLED public sector. Deliver and forecast revenue, direct sales activities, build pipeline, coach reps on value-based selling, and negotiate deals to achieve quarterly and annual targets.

Lead post-silicon failure analysis and validation for complex SoCs/ASICs. Define post-silicon plans, capture and analyze electrical measurements (eye diagrams, jitter, BER, PDN), improve yield/reliability, support bring-up, manufacturing, field issues, and contribute to test/observability software (Python/C++).

Design, develop, and maintain Salesforce solutions including Apex, Visualforce, LWC, integrations (REST/SOAP), and CI/CD. Lead technical best practices, troubleshoot issues, collaborate with business partners, document designs, and adopt new Salesforce features and AI tooling to support GTM IT initiatives.

Build and maintain UI and REST API automation using Playwright/Selenium/Pytest and Python; integrate tests into CI/CD (Jenkins, GitHub Actions); run tests in Docker and cloud (AWS/GCP/Azure); apply LLMs/generative AI to accelerate test creation and triage; reduce flakiness and expand coverage; collaborate with developers and QA; support enterprise networking and platform products. Hybrid role (3 days onsite, San Jose).