Top Tech Jobs & Startup Jobs

Lead ASIC STA methodology, architecture, and verification for advanced-node chips. Define timing constraints, drive timing closure and ECOs, oversee parasitic extraction and OCV methodologies, mentor teams, create standards, and collaborate with packaging, hardware, and vendor partners to meet power, performance, and area goals.

Lead ASIC implementation with a focus on Design-for-Test (DFT): define DFT architecture, coordinate with RTL and physical design teams, drive ATPG and EDA tool use, own test infrastructure and post-silicon validation, collaborate on timing closure and electrical planning, and develop reusable DFT IP and verification flows.

Lead end-to-end DFT flow architecture and build scalable DFT CAD infrastructure from RTL through insertion, ATPG, simulation, and reporting. Develop regression frameworks with orchestration, monitoring, logging, and recovery. Drive AI-driven automation for log analysis and failure triage, collaborate across RTL/PD/validation, set metrics and dashboards, evaluate new tools, and mentor engineers.

Lead and architect ASIC design verification environments for high-end switching products. Develop testbenches, simulation models, test plans, directed and random tests, and coverage. Collaborate across design, architecture, software, and post-silicon teams to debug silicon and customer issues. Mentor junior engineers and ensure comprehensive verification coverage.

Lead ASIC design verification for high-end switching: architect and maintain block/cluster/top-level DV environments, develop simulation models, test plans, directed and random tests, and coverage. Build testbench components (scoreboards, agents, sequencers, monitors), run multi-chip/system simulations and performance analysis, support post-silicon bring-up and customer issue debugging, contribute to chip architecture discussions, and mentor junior engineers.

Design, develop, and qualify integrated silicon photonics devices (modulators, photodetectors, grating couplers) for optical transceivers. Create layouts, test and characterize devices (including high-speed), collaborate with foundries and IC designers, deliver device models, and support manufacturing optimization and reliability qualification.

Lead ASIC DFT efforts across RTL and physical design teams: define and implement post-silicon strategies, develop and integrate DFT IP (ATE, in-system test, debug, diagnostics), enable ATPG flows and gate-level simulation, and drive post-silicon validation and testability from first silicon to production.

Lead technical program efforts for vendor IPs, standard cells, and PDKs across architecture through tape-out and post-silicon. Align stakeholders, manage vendor/foundry engagement, ensure integration/validation/versioning, define QA/release platforms, debug PDKs, and enable documentation and best practices for physical design flows.

Lead and consult on complex mechanical engineering projects across multiple products. Define standards, materials, DFM and BoM strategies, oversee prototyping, testing, failure analysis, supplier selection/onboarding, and collaborate with customers and internal teams to deliver manufacturable, cost-effective hardware platforms.

Lead mechanical engineering efforts across multiple products and teams, guiding junior engineers, supplier collaboration, DFM and BoM strategy, testing, failure analysis, prototyping, and reliability. Define standards, vet materials and suppliers, address supply chain and quality issues, and drive cost-saving value engineering for next-generation hardware platforms.