Top Tech Jobs & Startup Jobs

Lead development of system-level behavioral models and link simulations for silicon photonics transceivers. Perform link-budget and channel modeling, optimize TX/RX architectures and DSP, debug simulations, correlate pre- and post-silicon results, and collaborate cross-functionally to produce IBIS-AMI models and documentation through product release.

Lead mixed-signal ASIC design for silicon photonics driver ICs supporting 100G–400G per lambda. Define full-chip electrical specs, design high-speed datapaths and control circuits, author verification/test plans, debug silicon and system issues during bring-up, drive yield improvements, and mentor analog, digital, and validation engineers across cross-functional teams.

Lead DFT/DFx architecture and RTL implementation for next-generation ASICs. Define test strategies, develop RTL quality checks, support tape-out sign-off, post-silicon bring-up, debug, yield and production test support. Mentor and lead engineers to deliver reusable test and debug methodologies.

Design and develop pre-silicon emulation environments and infrastructure. Implement tests to generate complex traffic and performance scenarios, debug RTL/emulation prototypes, and collaborate with design, DV, power, and post-silicon teams and emulation vendors to catch issues before silicon.

Lead verification strategy and execution for silicon photonics ASICs and high-speed transceivers. Define methodologies, lead block- and chip-level verification for SerDes, drivers, TIAs and related IPs, mentor engineers, debug silicon and system-level issues, and support post-silicon bring-up and integration performance optimization.

Lead DFT solutions for next-generation ASICs: define and implement SSN and hierarchical DFT architectures, perform scan insertion and ATPG (stuck-at, transition, cell-aware, path delay), run gate-level SDF simulations, integrate/verify DFT IP, support post-silicon debug and diagnosis, and automate test flows using Python/Tcl/C++.

Lead ASIC STA methodology, architecture, and verification for advanced-node chips. Define timing constraints, drive timing closure and ECOs, oversee parasitic extraction and OCV methodologies, mentor teams, create standards, and collaborate with packaging, hardware, and vendor partners to meet power, performance, and area goals.

Lead ASIC implementation with a focus on Design-for-Test (DFT): define DFT architecture, coordinate with RTL and physical design teams, drive ATPG and EDA tool use, own test infrastructure and post-silicon validation, collaborate on timing closure and electrical planning, and develop reusable DFT IP and verification flows.

Lead end-to-end DFT flow architecture and build scalable DFT CAD infrastructure from RTL through insertion, ATPG, simulation, and reporting. Develop regression frameworks with orchestration, monitoring, logging, and recovery. Drive AI-driven automation for log analysis and failure triage, collaborate across RTL/PD/validation, set metrics and dashboards, evaluate new tools, and mentor engineers.

Lead and architect ASIC design verification environments for high-end switching products. Develop testbenches, simulation models, test plans, directed and random tests, and coverage. Collaborate across design, architecture, software, and post-silicon teams to debug silicon and customer issues. Mentor junior engineers and ensure comprehensive verification coverage.