Top Tech Jobs & Startup Jobs

Lead development and execution of pricing and monetization strategies across hardware and software portfolios. Perform market and competitive analysis, model price elasticity and willingness-to-pay, support annual pricing reviews, build scalable pricing capabilities and tools, and collaborate cross-functionally with product, finance, sales, and GTM teams.

Lead DFT emulation strategy and architect emulation environments (Palladium/Veloce/Zebu). Drive pre-silicon test plan execution, validate scan/MBIST/JTAG architectures, collaborate with RTL/physical/ATPG teams, troubleshoot emulation and post-silicon pattern conversion, and mentor engineers to enable successful silicon bring-up.

Lead ASIC design verification for high-end switching products: architect and maintain block-to-top DV environments, develop simulation models, tests, coverage, and testbench components; perform multi-chip/system simulation, performance analysis, and debug post-silicon bring-up with cross-team collaboration.

Lead development and execution of pricing and monetization strategies across hardware and software products. Perform competitive and market analysis, pricing analytics, customer willingness-to-pay studies, and annual pricing reviews. Partner cross-functionally to build scalable pricing capabilities, tools, and packaging that drive revenue, cross-sell, and upsell.

Lead Tier 3 escalation support for Cisco Contact Center Enterprise: isolate and resolve critical P1/P2 incidents, analyze traces and logs with RTMT/Wireshark, coordinate cross-team incident response, mentor engineers, and help deploy AI-enabled and cloud-integrated contact center features. May join on-call rotation.

Design, implement, and operate distributed, database-backed storage services and versioned APIs; lead medium-sized features end-to-end; remain hands-on in Go/C++ to debug and improve reliability, performance, and security; coordinate across product, SRE, security, and platform teams; act as production escalation lead, run postmortems, and mentor junior engineers.

Develop and validate ASIC package designs focusing on signal and power integrity for high-speed interfaces. Perform SI/PI simulations (pre/post-layout), post-layout extraction, layout reviews, and collaborate with layout, vendors, and system partners to meet power, performance, and area targets for advanced 2.5D/packaging technologies.

Develop and validate block-level and full-chip timing constraints (SDCs), perform static timing analysis using industry tools, collaborate with front-end/back-end and DFT teams to close timing across modes, and contribute to RTL, microarchitecture, and clocking design and documentation for next-generation networking ASICs.

Lead SOX readiness risk assessments and execute SOX program activities for key financial processes. Partner with finance, IT, project teams, and external auditors to evaluate control design, communicate responsibilities, and ensure continued compliance as systems and processes change.

Technical leader for Splunk IAM engineering driving architecture, security, and scalable distributed systems. Translate strategy into technical direction, lead cross-team projects, mentor engineers, contribute production-grade code, run threat modeling, improve observability and on-call reliability, and prototype complex integrations and PoCs.