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Leads complex cross-functional projects and process improvements for Cisco’s Failure Analysis and Prevention team. Responsibilities include defining project scope, schedules, metrics, budgets, risks, and mitigation plans; managing delivery and stakeholders; coordinating vendors; driving organizational change; training team members; and evaluating results to improve productivity, quality, and product outcomes.

Sell Splunk solutions to large enterprise accounts by managing complex, multi-stakeholder deal cycles. Prospect C-suite buyers, craft account strategies, advise on security, observability and cloud/SaaS adoption, lead negotiations, integrate CRM with BI for sales optimization, and collaborate cross-functionally to drive revenue and long-term customer value.

Leads architecture, definition, design, verification, and productization of high-performance mixed-signal ASICs, subsystems, and DFT frameworks. Owns project-level design methodology, develops reusable designs and automated flows, and collaborates with library, process, physical design, test, operations, vendors, and IP suppliers. Preferred expertise includes SoC DFT architecture, at-speed scan, MBIST, BISR, boundary scan, and parametric testing for analog and mixed-signal blocks.

Pre-sales Solutions Engineer partnering with enterprise account teams to design, demo, and configure Cisco solutions (switching, routing, wireless, data center, security, collaboration). Act as trusted technical advisor, align solutions to customer business needs, support proposals, and collaborate with architects and account managers.

Lead system- and board-level design for hyperscaler switches: define specs, create schematics/PCB, FPGA/ASIC design and bring-up, debug high-speed interfaces, coordinate across ASIC, SI, software, diagnostics, manufacturing, and supplier teams to resolve design issues.

Develop and maintain ASIC design verification environments. Build testbenches, write test plans and testcases, debug regressions, implement functional and code coverage, and verify complex SoC blocks using simulation, emulation, and AI-assisted methods to drive verification closure.

Design and validate high-speed hardware for Cisco 8000 series routers, driving product lifecycle from architecture through manufacturing. Responsibilities include board design using Cadence/Allegro/Concept, layout guidance, lab bring-up, debug with analyzers/oscilloscopes, writing specs and test plans, and cross-functional collaboration with ASIC, software, mechanical, manufacturing, and signal integrity teams.

Lead hardware board and system design for Cisco Edge and Access routing products from architecture through bring-up, validation, qualification, and production. Drive hardware specifications, schematic capture, and cross-functional coordination with software, diagnostics, manufacturing, and test teams to ensure product readiness.

Design and verify high-performance, multi-layer PCBs for next-generation networking hardware. Lead full board lifecycle: schematic/layout, high-speed signal and power integrity debugging, failure analysis, test-plan development, and design reviews to ensure product reliability.

Develop and refine mechanical components and systems for Cisco hardware platforms. Apply analytical problem-solving to engineering challenges, collaborate with cross-functional teams, conduct mechanical and thermal design testing, and debug issues. The role requires current undergraduate enrollment in mechanical engineering or a related field, continued enrollment after the internship, and experience with 3D MCAD tools. Familiarity with Python, MATLAB, or C++ for automation and data analysis is preferred.