Top Tech Jobs & Startup Jobs

Design, develop, and maintain large-scale test automation for coherent optical transceivers; execute tests on product releases; collaborate with developers to resolve defects; document test results and publish software release notes to ensure hardware and software specifications are met.

Lead architecture and development of embedded firmware for coherent optical transceivers. Design algorithms and low-level C/C++ code for RTOS and bare-metal CPUs, drive cross-functional requirements with hardware, ASIC, DSP, and optics teams, participate in system bring-up, debugging, manufacturing transition, and customer technical discussions.

Lead bring-up, verification, calibration, and production-test optimization of coherent optical transceivers. Collaborate with DSP, software, hardware, and PIC teams to maximize performance, minimize power and size, and improve manufacturing yield and test automation.

Lead product management for Acacia client optics, driving requirements, roadmaps, lifecycle, manufacturability, supply chain, go-to-market, and cross-functional engineering and operations collaboration to deliver high-speed optical interconnect products.

Lead ASIC physical design for fullchip RTL-to-GDSII implementation: floorplanning, partitioning, clock/power planning, place-and-route, timing and power signoff, verification, and methodology improvements while collaborating with RTL, DFT, EDA vendors, foundry and post-silicon teams.

Lead RTL-to-GDSII physical implementation and methodology improvements, covering synthesis, floorplanning, P&R, CTS, STA, power integrity, sign-off flows, ECOs, and EDA tool/flow evaluation and automation across advanced process nodes.

Serve as Cisco Capital's strategic financial advisor for Global Enterprise accounts: structure complex financing deals, lead executive engagements, coordinate billing and operations, influence cross-functional teams, and exceed attachment financing revenue targets.

Drive revenue growth across a geo-based territory by engaging existing customers and new prospects. Develop enterprise solutions with partners, manage full sales cycle, meet license/support/service revenue targets, and deliver high-velocity transactional outcomes while building C-level relationships.

Lead CDC/RDC methodology for ASIC subsystems: design and implement CDC-aware RTL, define CDC check flows and SDC constraints, perform static glitch and gate-level analysis, review/approve constraints and waivers, and collaborate with CAD to productionize robust, reusable silicon designs.

Define and architect DFx and test solutions for ASICs and subsystems. Lead RTL implementation and quality checks, develop ATE screening, in-system test, debug and diagnostics, and drive reusable test/debug methodologies for advanced nodes and packaging in collaboration with cross-functional teams.