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Perform electrical characterization and reliability testing of advanced semiconductor devices and materials. Develop testing methodologies, analyze measurement data, investigate failures, support test structure and experimental setup development, and correlate results with device physics and process behavior. Collaborate with process, device, product engineering, and R&D teams while reporting findings and recommending device optimization improvements.

Coordinates employee lifecycle processes, onboarding, offboarding, personnel records, recruiting logistics, interview scheduling, and candidate communication. Supports workplace operations by managing facilities, vendors, office inventories, and employee events. Helps maintain a welcoming employee experience through internal communications and recognition programs, while improving People and workplace processes. Handles confidential information discreetly and collaborates with IT, Finance, recruiting, and other teams.

Leads semiconductor process integration and wafer operations within R&D lines. Develops integration processes for next-generation devices, manages R&D line expansion with facility and equipment teams, plans experiments, coordinates resources, and provides technical leadership for process development and technology deployment to manufacturing fabs. Requires a Ph.D. in a relevant science or engineering discipline and 3–5 years of semiconductor process integration experience.

Develop and optimize hardware and software test strategies, programs, patterns, and methods for memory, compute, and system testing. Procure and scale test hardware across internal and partner environments, execute Design of Experiments, analyze data, debug device failures, identify root causes, and improve testability, quality, process feedback, and product yield. The role requires semiconductor testing expertise, strong collaboration and communication skills, and the ability to operate effectively in a fast-paced R&D environment.

Own the architecture, RTL implementation, verification, timing closure, and tapeout of a custom UHBM-based 3D DRAM memory controller for an AI accelerator. Lead scheduler, command/data paths, ECC, refresh, power management, training, initialization, and distributed TSV interface design. Drive PPA optimization, physical-design collaboration, SoC integration, formal verification, post-silicon bring-up, technical documentation, and mentoring while coordinating with architecture, packaging, foundry, verification, and memory technology partners.

Owns and evolves AWS/Linux infrastructure supporting semiconductor design and EDA workloads. Responsibilities include administering enterprise Linux systems, high-performance cloud storage, virtual desktop environments, remote access, FlexLM licensing, identity integration, security hardening, system performance, and infrastructure as code. The role also develops automation using Bash and Python and supports AWS networking, IAM, EC2, and engineering computing environments.

Leads full-chip and subsystem physical design for a next-generation 3D-memory AI accelerator, from netlist ingestion through GDSII signoff. Owns floorplanning, placement, CTS, routing, timing, power integrity, signal integrity, physical verification, DFT, low-power implementation, and 3D-IC integration. Partners with architecture, synthesis, STA, packaging, foundry, and design-service teams while managing physical design engineers, tapeout readiness, methodology, tool strategy, and successful silicon productization.

Own the ALD and PEALD process roadmap from concept through qualification and 300mm fab-scale industrialization. Lead a small process engineering pod, set priorities, review experiments and data, mentor engineers, and resolve technical challenges. Partner with equipment vendors and cross-functional teams, define hardware requirements, evaluate thin-film metrology, and present technical trade-offs to senior leadership. The role requires deep deposition expertise, process-hardware correlation knowledge, and experience qualifying production-scale processes.