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Lead development and execution of verification strategies and reusable UVM/SystemVerilog testbenches. Implement tests, manage regressions, gather coverage, and debug issues across simulation, emulation, gate-level and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation to improve verification infrastructure and methodology.

Bring up and validate next-generation AI hardware systems; debug complex hardware-software integration issues using logs, telemetry and diagnostics; build automation, testing, and tooling to improve validation, observability, and debugging workflows; collaborate with hardware teams to reproduce, triage, and resolve failures as systems move toward production.

Implement and scale LLM training, fine-tuning, and post-training techniques (RL-based). Build evaluation and data pipelines, debug ML stack issues, optimize training/inference workflows, and ship maintainable ML infrastructure code.

Lead technical direction and architecture for a multi-region Inference Cloud Platform. Define failure domains, service boundaries, and SLO-driven reliability. Optimize latency, throughput, and capacity for high-QPS ML inference workloads; implement graceful degradation (circuit breaking, backpressure, load shedding). Write and review production code, drive observability and incident response, and coordinate cross-team platform decisions. Mentor engineers and set long-term platform strategy.

Owns end-to-end technical programs for site and data center operations supporting AI cloud and customer deployments. Single-threaded owner across hardware, AI cloud, network/storage, and facilities; drives site readiness, installation, commissioning, incident reviews, KPIs (availability, MTTR/MTTD, capacity), executive dashboards, governance, and risk tracking.

Lead capacity planning and fleet strategy for the Inference Service: build rolling forecasts, support datacenter bring-up, decide model/cluster allocation, run utilization reporting, drive capacity tool adoption, coordinate cross-functional execution, and manage incident postmortems.

Design and implement verification strategies and reusable SystemVerilog/UVM testbenches; create tests, run regressions, collect coverage, and debug across simulation, emulation, and silicon bring-up. Collaborate with architects, RTL, physical design, firmware, and validation teams while improving verification infrastructure and methodologies.

Lead front-end RTL engineer responsible for functional specification, micro-architecture, RTL development, synthesis, and integration. Manage external ASIC vendors, collaborate with PD, verification, DFT, software and system teams, and debug silicon-level functional, timing, and power issues during bring-up to meet PPA and test coverage goals.

Build and maintain reproducible inference benchmarks (tokens/sec, time-to-first-token, latency, TCO), track GPU/kernel optimizations and quantization impacts, maintain competitive pricing models across inference providers, produce actionable competitive analyses for Sales and Product, and represent Cerebras in third-party benchmarking and industry monitoring.

Lead Cerebras's model portfolio: decide which models ship, set quality standards and benchmarks, partner with model labs and open-source maintainers, drive model launches, enable customers, prioritize optimizations, and coordinate cross-functional teams to maximize inference performance and adoption.