Top Tech Jobs & Startup Jobs

Support data center acquisition by sourcing colocation, powered shell, land+power, and expansion opportunities; conduct outreach to brokers and owners; build and manage a CRM pipeline; perform market screening and early diligence; validate provider claims; organize diligence materials; track deal stages, MW capacity, timelines, and risks; and improve sourcing workflows and qualification frameworks.

Lead microarchitecture and front-end RTL design for wafer-scale AI chips. Define functional specs, develop RTL, integrate IP, collaborate with PD/DFT/software teams, debug silicon bring-up, and meet PPA goals.

Develop, optimize, and validate high-performance ML and linear-algebra kernels for Cerebras wafer-scale hardware. Implement low-level assembly and a C-like DSL (CSL), model and analyze performance, build testing methodologies, and collaborate with chip and system architects to maximize compute utilization for state-of-the-art AI and HPC workloads.

Design, implement, optimize, and validate high-performance ML and linear algebra kernels for Cerebras hardware. Develop low-level assembly and CSL routines, use mathematical performance models, create unit/system tests, and collaborate with chip and system architects to maximize compute utilization and scale kernels for state-of-the-art AI/HPC workloads.

Design and implement high-performance distributed runtime components for large-scale training and inference. Optimize data and communication pipelines, enable scalable multi-node execution, collaborate with ML and compiler teams, diagnose performance issues via profiling, and contribute to system architecture and roadmap for cutting-edge AI workloads.

Lead and build a research-focused ML team to develop and adapt advanced ML algorithms (post-training, RL, pretraining, sparsity, dataset curation) for deployment on Cerebras hardware, collaborate across teams and external partners, and guide production training, tuning, and evaluation to drive hardware-software co-design and performance optimization.

Lead corporate FP&A for a newly public AI hardware company: build planning, forecasting, reporting, KPI dashboards, revenue forecasting, G&A business partnering, and automation to deliver investor-grade insights and scalable finance operations.

Design and analyze 3D integrated ASIC/SoC products, including packaging, power, clock, cooling, and 3D die-stacking. Perform block and full-chip physical verification (DRC/LVS), IR/EM and SI/PI analysis, optimize power/performance/area, enhance flows with Tcl/Python scripting, and collaborate with RTL and architecture teams on novel 3D integration R&D.

Develop and implement verification strategies and reusable SystemVerilog/UVM testbenches; write tests, manage regressions, collect coverage, and debug issues across simulation, emulation, and silicon bring-up while collaborating with architects, RTL, firmware, and software teams.

Build and maintain CI/CD pipelines and artifact lifecycle systems, provision and optimize cloud (AWS) CI infrastructure, troubleshoot build and pipeline issues, improve developer tooling and build/test infrastructure, support code review/workflow improvements, participate in on-call incident response, and contribute to AI tooling to boost engineering productivity.