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Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Develop timing constraints, collaborate on verification and physical design, support timing closure, and debug post-silicon issues with hardware, firmware, and software teams. Contribute to power-aware performance optimization for Host Fabric Interface subsystems used in AI and HPC networking.

Develop and maintain AI-based ASIC verification automation flows, regression infrastructure, dashboards, reporting tools, and triage automation. Build scripts and integrations using Python, Perl, Tcl, shell scripting, and Make. Support simulation, coverage, lint, formal, emulation, continuous integration, EDA tool integration, and distributed compute infrastructure. Debug automation, tool, runtime, licensing, queue, and workflow issues while improving verification reliability, reproducibility, and efficiency across geographically distributed engineering teams.

Develop and support hardware and software manufacturing test processes for networking products produced through contract manufacturers. Responsibilities include designing PCB test fixtures, creating functional test procedures, troubleshooting production and RMA failures, supporting NPI transitions, training manufacturing teams, managing test software releases, performing failure analysis, and maintaining test documentation. The role also involves hands-on electronic troubleshooting, assembly rework, prototype support, and collaboration between engineering and manufacturing.

Lead and grow the RTL design engineering team responsible for next-generation networking ASICs. Own RTL delivery schedules, coordinate design verification, emulation, and physical design dependencies, manage timing-closure and tape-out readiness, identify schedule risks, and allocate resources. Develop headcount and organizational plans, lead hiring, and scale globally distributed engineering practices while contributing hands-on expertise in microarchitecture, RTL design, synthesis, verification, and PPA optimization.

Design and implement Verilog/SystemVerilog RTL for high-speed ASIC data paths and packet processing. Collaborate on verification, timing constraints, physical design, post-silicon validation, system debugging, performance optimization, and power-aware Host Fabric Interface designs. The role focuses on Ethernet, networking protocols, high-performance computing, AI interconnects, and SoC development.

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Leads verification closure for ASIC modules, subsystems, and SoCs used in AI and HPC networking. Defines verification strategies, develops UVM testbenches, executes functional tests, manages regression and coverage closure, debugs RTL issues, and collaborates with design, software, emulation, hardware, and post-silicon teams. Provides technical leadership, mentoring, coding guidance, and promotes AI tools for verification productivity.

Lead verification closure for complex ASICs and SoCs used in AI and high-performance computing networking. Define verification strategies, develop UVM/SystemVerilog testbenches, execute functional testing, debug RTL failures, and close functional and code coverage. Guide block, subsystem, and SoC verification while collaborating with design, software, emulation, hardware, and post-silicon teams. Mentor engineers, establish verification guidelines, and promote AI tools to improve team productivity.

The Senior Account Manager will develop and execute sales strategies for HPC and AI networking solutions across higher education and automotive accounts. Responsibilities include prospecting, building customer relationships, managing Salesforce pipeline activity, meeting quotas, collaborating with channel and OEM partners, presenting technical solutions, and providing market feedback. The role requires a self-generating hunter mentality, grant proposal experience, technical knowledge of network interconnects, and up to 50% travel for conferences and customer meetings.

Perform SI simulations and measurements for high-speed interfaces (PCIe, Ethernet), correlate lab results with models, provide design guidelines, review PCB/platform layouts, and support cross-functional teams through product development to production.