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The Senior RTL Design Engineer will design and implement components for next-generation AI processors, collaborating with various engineering teams to ensure performance and correctness while focusing on low-power, high-performance designs.

Design and verify NVM IP macros and circuits for Mythics analog compute-in-memory products. Develop RNM/functional models, HV generators, x/y-paths, peripherals, and handshake circuits with analog compute blocks. Lead full-chip simulation, tapeout support, layout supervision, silicon debugging, and coordinate validation and backend teams to qualify production releases.

Design, optimize, and verify NVM circuit IP and full-chip simulations for analog compute engines. Develop RNM/functional models (Verilog-A/SystemVerilog/Python), collaborate with validation and backend teams, and support tapeout, silicon debug, and production qualification.

Develop and own DSP and algorithm blocks to mitigate analog impairments for analog compute-in-memory: calibration, non-linearity compensation, offset correction, and error estimation. Build Python frameworks and firmware, improve simulation fidelity, correlate silicon and simulation errors, and lead silicon bring-up, characterization, and productization with cross-functional teams.

Own full-cycle recruiting for technical and leadership semiconductor roles. Partner with hiring managers and executives on hiring strategy, compensation, and org design. Source niche passive candidates, manage high-volume confidential and executive searches, drive offers and negotiations, mentor junior recruiters, and improve TA processes and employer branding.

Lead and build Mythic's marketing function end-to-end: define brand and category narrative, create vertical and product positioning, build demand-generation and sales enablement assets, recruit and scale a full marketing team, and represent the company externally across data center, automotive, robotics, and defense markets.

Lead end-to-end systems engineering to turn Mythic analog compute chips into validated, customer-ready cards, modules, and platforms. Build and scale validation teams, drive hardware/software co-validation, own test infrastructure and automation, support OEM/hyperscale qualification, and feed field learnings into product and architecture decisions.