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Build simulation and modeling infrastructure for AI inference accelerators before silicon availability. Develop analytical performance models, functional and timing simulators, virtual platforms, and software integrations. Validate functionality and performance against reference implementations and hardware, improve simulator speed and usability, and create automated regression coverage. Collaborate with hardware, compiler, firmware, runtime, performance, and test engineers to support architecture exploration and realistic software workloads.

Owns AI-assisted engineering across accelerator software teams, embedding agentic workflows into coding, debugging, triage, testing, documentation, CI, and silicon-debug processes. Builds shared agent tooling, maintains evaluations, measures productivity gains, and establishes standards for reliable AI-native development. Requires expert experience with Codex, Claude Code, LLM APIs, evaluations, and adopted developer tooling, plus strong systems or infrastructure credibility.

Lead the architecture, design, verification, physical implementation, tape-out, validation, and production ramp of high-performance AI inference ASICs. Drive PPA optimization, memory subsystem design, hardware/software co-design, and relationships with foundries, IP vendors, and EDA providers. Recruit and mentor the ASIC team while shaping the company’s silicon roadmap and execution methodology.

Define next-generation AI inference accelerator architectures through architectural exploration, performance modeling, hardware/software co-design, and ASIC specification. Evaluate transformer, MoE, sparse, long-context, and emerging AI workloads; model latency, throughput, memory, bandwidth, power, area, cost, and scaling; define subsystem interfaces; and guide the product roadmap in collaboration with software, ML, systems, and silicon teams.

Owns synthesis methodology, timing closure, constraint development, QoR optimization, and implementation readiness for advanced AI accelerator ASICs. The role transforms RTL into implementation-ready netlists, leads physical-aware optimization and timing budgeting, collaborates across architecture, verification, DFT, and backend teams, and provides technical leadership to external implementation partners. Responsibilities also include developing Tcl and Python automation and applying AI to improve timing analysis, regression, debugging, and engineering workflows.

Develop and lead verification strategies for AI inference ASICs, including SystemVerilog UVM environments, simulation testbenches, directed and constrained-random testing, coverage closure, debugging, and root-cause analysis. Collaborate with design, architecture, software, FPGA, and emulation teams across pre-silicon and post-silicon validation. Manage verification schedules, deliverables, and risk mitigation while helping ensure functional correctness and performance.

Lead ASIC/SoC IP and subsystem development from microarchitecture through RTL signoff. Design parameterized SystemVerilog RTL, own PPA targets, and lead lint, CDC/RDC, DFT, synthesis, and timing activities. Architect interfaces, DMA, coherency, and HBM/DDR integration while collaborating with architecture, verification, and physical design teams. Improve design methodologies, mentor engineers, lead reviews, support post-silicon debug, and contribute automation flows.

The Senior Software Engineer will develop high-performance software for executing open-source LLMs on custom hardware, focusing on optimizations and efficient libraries primarily in C++.

Own technical product planning for AI inference software: define requirements across model coverage, numerics, inference engine and serving-stack features, roadmap planning, ecosystem engagement, documentation, lifecycle management, and automation using agentic AI. Translate model and system trends into engineering scope and partner with engineering and GTM teams to deliver a managed inference service.

Lead technical product planning for silicon and rack-scale inference systems: write PRDs, define SKU and lifecycle strategy, translate customer and market signals into engineering requirements, perform performance and cost modeling, maintain competitive and partner intelligence, and streamline product planning using agentic AI.