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Design, deploy, and maintain on-prem AI infrastructure and agentic systems. Build GPU clusters, model serving, vector DB-backed RAG pipelines, fine-tune and deploy models, implement governance (MCP), and automate CI/CD and monitoring to integrate AI capabilities into enterprise workflows.

The intern will develop and validate storage test software, focusing on coding, debugging, and creating technical documentation for tools in semiconductor technology.

Support SSD performance test and analysis by developing and executing test plans, recording results, identifying issues, analyzing performance data with scripts/tools, maintaining test data, and collaborating with cross-functional teams to improve SSD quality.

Lead design and execution of test plans for PCIe and NVMe eSSDs, manage testing progress, collaborate with teams to resolve issues, and enhance product quality.

The Sr. Principal FTL Engineer will design and implement Flash Translation Layer for SSDs, perform firmware evaluations, and conduct debugging and integration.

The Program Manager will oversee enterprise SSD development by coordinating with various teams, managing schedules, and providing project updates while ensuring smooth communication between teams.

The role involves designing and automating test plans for enterprise SSDs and server storage systems while collaborating with development teams to resolve defects and ensure product quality.

Design, develop, and automate test plans for SSD products, ensure product quality, and collaborate with teams for reliable solutions during the development cycle.

Assist engineers with RTL review, DFT activities, synthesis, timing analysis, and debugging design issues, while collaborating with team members.

Design, implement, and debug Flash Translation Layer (FTL) and real-time embedded firmware for SSD products. Perform firmware code reviews, integration, performance profiling, validation, failure analysis, and corrective actions in collaboration with stakeholders. Contribute to system-level debugging and optimization for multi-core ARM-based controllers.