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Own end-to-end embedded software program execution across firmware, drivers, bootloaders, hardware, architecture, compiler, runtime, and validation teams. Align software milestones with tape-out, silicon and board bring-up, validation, and customer delivery. Identify and resolve cross-team risks, manage schedules and operating cadence, support platform enablement, and coordinate distributed engineering teams and external partners for AI accelerator deployments.

Leads customer and partner solution development for AI acceleration platforms, including system design, benchmarking, performance tuning, proof-of-concepts, deployment, technical pre-sales, reference applications, partner enablement, and ecosystem collaboration. Influences product roadmaps while integrating AI hardware, software, systems, and customer workloads for edge, datacenter, and embedded applications.

The Staff DFT Engineer at EnCharge AI will define and implement the DFT architecture for AI accelerators, manage DFT constraints, generate test patterns, and optimize for Edge AI applications while collaborating with ATE teams for silicon debugging.

Lead the DFT architecture and strategy for complex SoCs, overseeing scan/ATPG, MBIST/logic BIST, IJTAG/boundary scan, post-silicon ATE bring-up, and edge-specific IST/POST to ensure manufacturability, reliability, and minimal power/area impact.

Own top-level physical integration and signoff for very large SoCs from floorplan to tapeout. Architect hierarchical physical verification flows, execute full-chip DRC/LVS/ERC/antenna/ESD/latch-up signoff, resolve integration bottlenecks with PD/STA, collaborate with foundries on rule co-optimization, and automate PV/integration flows to accelerate tapeout.

The Senior NPU Architect will design and optimize architecture modules for AI accelerators, collaborating with teams to enhance performance for AI/ML workloads.

Lead development and optimization of a highly automated RTL-to-GDSII and timing signoff flow. Own Innovus methodology and Tempus STA integration, reduce turnaround time with Python/Tcl automation, interface with Cadence, debug tool/database issues, and mentor PD and timing teams to ensure robust, high-performance physical implementation for AI accelerators.

Seeking a Senior Physical Design Engineer with expertise in chip-level implementation, EDA tools, and low-power design to enhance AI hardware capabilities.