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The Customer Programs Manager advocates for customers of a CMOS product line, driving program execution, aligning internal teams, and managing customer requirements and communication effectively.

Entry-level design verification role for new college graduates to develop and execute verification plans for RISC-V processors/cores. Responsibilities include reviewing specs, developing testbenches, creating tests and test plans, debugging test cases, closing coverage, and contributing to modeling, flow, and methodology development.

Perform design verification of RISC-V processors/cores including reviewing design/specifications, developing testbenches and test plans, creating and debugging tests, driving coverage closure, and developing modeling, flows, and methodologies for IP/SoC verification.

Perform design verification for RISC-V processors/cores: review design and RISC-V specifications, develop testbenches, create test plans and tests, debug test cases, drive coverage closure, build models, and develop verification flows and methodologies. Document processes and collaborate across teams to ensure robust IP/SoC verification.

Perform design verification of RISC-V processors/cores: review design/specs, develop testbenches and test plans, create and debug tests, close coverage, and develop modeling, flow, and methodology.

Oversee and optimize wet cleans processes: develop recipes, reduce variability, document procedures, start up and qualify processes/equipment, improve tool-to-tool matching, support CIP and SPC programs, troubleshoot yield/defect issues, and collaborate cross-functionally to meet quality, cost, productivity, and yield goals.

Lead RTL development and microarchitecture of an AI-enabled RISC-V CPU core, including vector and matrix engines. Drive design for performance, power, area, verification support, and SoC integration while collaborating with cross-functional teams to meet timing, reliability, testability, and power goals.

The role involves leading Silicon Photonic process integration, driving technology improvements, and collaborating with teams for project management. Requires strong leadership and technical skills.

Design and own RTL for AI-enabled RISC-V CPU cores including vector and matrix engines. Drive microarchitecture, performance/power/area trade-offs, support functional verification, and collaborate on physical design integration and validation.

The Associate Engineer is responsible for maintaining semiconductor manufacturing equipment, handling breakdowns, and following safety standards, while supporting 24/7 operations.