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Silicon Labs

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

Reposted 2 Months AgoSaved
In-Office
Austin, TX, USA
143K-266K Annually
Expert/Leader
143K-266K Annually
Expert/Leader
Hardware • Software
Lead design and integration of low-power wireless SoCs: define SoC-level power intent and clocking architectures, drive RTL for power/clock/reset controllers and interconnects, debug CDC/RDC/power/clock issues, collaborate across verification, backend, analog teams, and support silicon bring-up while mentoring small design teams.
Top Skills: AhbApbAxiCCpfGitLogic SimulatorsLogic SynthesisMethodicsPerforcePerlPower Analysis ToolsPythonRisc-VSystemverilogTclTiming ConstraintsUpfVerilogWaveform Browsers
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