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d-Matrix

Sr. Staff Design Verification Engineer

Reposted One Month AgoSaved
Hybrid
Santa Clara, CA, USA
175K-265K Annually
Senior level
175K-265K Annually
Senior level
Artificial Intelligence • Machine Learning • Software
The Design Verification Engineer will lead SoC verification cycles, utilizing methodologies like UVM/OVM, and contributing to innovative AI architectures.
Top Skills: CC++OvmSystemcSystemverilogUvm
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