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Design, implement, optimize, and validate high-performance ML and linear algebra kernels for Cerebras hardware. Develop low-level assembly and CSL routines, measure and tune performance, build testing methodologies, and collaborate with chip and system architects to maximize compute utilization for AI and HPC workloads.

Develop and maintain the architecture for Cerebras' Inference Cloud Platform, focusing on distributed systems, performance optimization, and technical direction. Responsibilities include coding, design reviews, and mentoring senior engineers.

The Deployment Engineer will manage AI inference clusters, optimizing deployment, capacity allocation, and ensuring reliability of pipeline operations across datacenters.

Manage AI compute clusters, monitor systems health, optimize resources, and troubleshoot technical issues, ensuring high performance for ML applications.

Lead a team in developing and scaling distributed inference systems for AI on Cerebras' hardware, ensuring reliability and performance while mentoring engineers.

The Sr. Technical Staff will validate silicon for wafer-scale engines, conduct high-speed interface testing, and develop automated regression tests. They will collaborate with engineering teams for hardware optimization, diagnosing issues, and ensuring compliance with design specifications.

Lead PCB design from specification through implementation, bring-up, qualification, and production. Own schematics, component selection, and layout. Perform lab bring-up, debugging, and automated benchtop test development. Collaborate with manufacturing, test, supply chain, ASIC, mechanical, signal integrity, power delivery, layout, embedded, and diagnostics teams.

The Performance Engineer - Inference will optimize model inference speed and throughput, debug low-level kernel performance, and develop tools to visualize performance data.

The Head of IT will build and manage the company's technology backbone, focusing on IT strategy, scaling, endpoint management, SaaS governance, and compliance while supporting rapid growth in a high-tech environment.

Lead development of test programs and ATE strategy for wafer-scale AI/ML accelerator chips. Design DFT and scalable wafer-level test methodologies, fault isolation, probe/load-board specs, characterization (di/dt, V-F), yield optimization, and cross-functional production debug.