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Lead architecture and design of power delivery from grid to chip for data center AI systems. Define roadmaps, specify rack- and board-level power hardware and firmware, drive vendor engagement, ensure reliability/efficiency, develop prototypes, validate designs, resolve complex hardware/firmware issues, and ensure industry compliance.

Lead development and deployment of system-level test (SLT) hardware and software for AI processors. Drive SLT workstreams from requirements through production readiness, develop test boards and automation, perform characterization and reliability screening, lead failure analysis and yield learning, collaborate with DFT, OSATs, and manufacturing, mentor junior engineers, and support production ramp and vendor engagements.

Lead post-silicon bringup and validation for high-performance AI chips. Develop and debug bare-metal C/C++ tests on FPGA/emulator and deploy on first silicon, build Python automated test frameworks, analyze failures, improve test infrastructure, and collaborate across teams to characterize and stabilize silicon.

The role involves leading the bring-up and characterisation of silicon devices, executing tests, and liaising with engineering teams to ensure correct operation under all conditions.

Lead and build an SLT test engineering team to develop system-level test capabilities for multi-die AI processors. Define manufacturing test solutions, design test fixtures, write production and characterization test programs on SLT platforms, collaborate across silicon, test, DFT and manufacturing teams, transfer solutions to volume manufacturers/OSATs, and support bring-up, failure analysis and yield improvement.

Lead global demand and supply planning, drive S&OP, forecasting, inventory optimization, NPI transitions, supplier partnerships, KPI reporting, process improvements, and mentor sourcing/planning teams to support AI infrastructure product delivery.

The role involves validating high-performance AI chips, developing tests in C/C++ and Python, leading team members, and optimizing validation processes.

We are seeking a Senior Post Silicon Validation Engineer to validate high-performance AI chips, develop validation tests, and collaborate with cross-functional teams for successful product introduction.

The Principal Power Engineer will lead power delivery architecture development, oversee hardware and firmware from grid to chip, and ensure compliance with performance standards.

Drive automation-based validation execution for AI hardware platforms, defining validation strategies and ensuring system readiness across blade and rack levels.