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Reposted One Month AgoSaved
Hybrid
Chandler, AZ, USA
Senior level
Senior level
Hardware • Software
Lead functional verification for mixed-signal ASICs including verification planning, UVM testbench development, constraint-random and directed tests, coverage and failure analysis, digital/mixed-signal modeling, gate simulations, and regression/debug infrastructure.
Top Skills: AvmGate-Level SimulationMixed-Signal ModelingOvmSystemverilogTestbench DevelopmentUvmVeraVerilogVerilog AssertionsVhdl
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