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Own and develop CAD automation infrastructure and Python-based tools to standardize project setup, automate design flows, manage design data and revisions, integrate/customize EDA tools, build regression/validation frameworks, and collaborate with design, CAD, IT, and vendors to improve design productivity and scale.

Lead functional verification for mixed-signal ASICs including verification planning, UVM testbench development, constraint-random and directed tests, coverage and failure analysis, digital/mixed-signal modeling, gate simulations, and regression/debug infrastructure.