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Perform layout and verification of high-performance mixed-signal CMOS ICs using Cadence Virtuoso XL and Mentor Calibre. Collaborate with circuit designers to create topological layouts, solve layout issues, apply device matching and signal conditioning/protection techniques, plan and integrate layouts, and perform block- and chip-level routing using assisted/automated tools.

The CAD Engineer role focuses on developing the automation foundation for silk design teams, enhancing EDA tools, and improving workflows across the organization.

Hands-on Senior AI Engineer who develops, prototypes, validates, and scales AI-enabled engineering capabilities across hardware, software, and firmware teams. Build RAG/LLM/agent workflows, integrate AI with repos, CI/CD, test and lab systems, establish rigorous evaluation and governance, and convert pilots into reusable engineering platforms.

Lead global engineering IT infrastructure supporting 1,000+ semiconductor design engineers. Own strategy, availability, performance, security, and scalability of Linux platforms, HPC/compute farms, enterprise storage, revision control, automation, observability, incident response, capacity planning, and cross-functional alignment to improve engineering productivity and tapeout reliability.

Design, simulate, and validate advanced I/O and ESD protection circuits. Develop silicon test structures for ESD and latch‑up evaluation, translate silicon data into design rules, release and maintain I/O libraries and models, drive chip‑ and block‑level ESD sign‑off, and lead cross‑team ESD and I/O reliability strategy.

Design and verify DFT features for mixed-signal SoCs: insert and verify Memory BIST and scan, generate ATPG patterns, perform gate-level verification, analyze test coverage and costs, and deliver patterns/support silicon bringup on ATE.

The Hardware Applications Engineer will lead customer design, system integration, PCB reviews, and training, ensuring optimal audio product performance and adoption.

As a Physical Design Engineer, you'll implement complex mixed-signal SoCs, optimizing timing and collaborating within a design team, while also developing design methodologies.

Lead the Silicon NPI team to bridge foundry process capabilities and mixed-signal design, resolve SOA/DRC/reliability issues, drive foundry engagement, improve yield and cost, and develop engineering staff.

Design and execute validation tests for pre- and post-silicon products, develop test plans and automation in CI, triage and debug hardware/software issues, and report quality metrics to stakeholders while collaborating with cross-functional teams.