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Reposted 23 Days AgoSaved
In-Office
San Jose, CA, USA
203K-230K
Senior level
203K-230K
Senior level
Big Data • Information Technology
The Principal Firmware Engineer will architect and develop firmware for SoC products, focusing on complex silicon solutions for server, storage, and networking applications.
Top Skills: CC++DoxygenGccGitMakePciePython
24 Days AgoSaved
In-Office
San Jose, CA, USA
Senior level
Senior level
Big Data • Information Technology
The Senior Digital Design Engineer will focus on front-end design and development of digital IP blocks, including RTL design, verification, and integration within ASIC systems, with a focus on high-performance standards.
Top Skills: CadenceDdrEda ToolsEthernetNvmePcie Gen3+PerlPythonRtlSynopsysTclUsb
Reposted 24 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Big Data • Information Technology
The Principal Firmware Engineer will architect and develop firmware for SoC and systems, ensuring customer needs are met and working on complex silicon products.
Top Skills: CC++DoxygenGccGitMakeMqx RtosPythonThreadx
Reposted 24 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Big Data • Information Technology
Architect and develop firmware and microcontroller subsystems for SoC and systems products, ensuring compatibility and implementing features effectively.
Top Skills: CC++DdrDoxygenEthernetGccGitInfinibandMakeMqx RtosNvmePciePythonThreadxUsb
Reposted 25 Days AgoSaved
Vietnam
Mid level
Mid level
Big Data • Information Technology
As a Senior Physical Design Engineer, you will lead physical implementation from RTL to GDSII for high-speed designs and ensure timing and power closure, involving collaboration across teams to resolve challenges in advanced technology nodes.
Top Skills: CalibreCxlEthernetIcc2InnovusPciePerlPythonRedhawkTclTsmc 3NmTsmc 5NmVoltus
Reposted 25 Days AgoSaved
In-Office
Bengaluru, Karnataka, IND
Senior level
Senior level
Big Data • Information Technology
The role involves developing and executing verification plans for PCIe and CXL protocols, collaborating with designers, and utilizing coding and protocol expertise for functional verification.
Top Skills: CxlPcieSocUvmVerification Ips
Reposted 25 Days AgoSaved
In-Office
Bangalore, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Big Data • Information Technology
Lead Software QA Engineer responsible for PCIe switch testing, developing test strategies, automation, and mentoring team members, ensuring quality in data-centric systems.
Top Skills: ConfluenceGitJIRAPython
Reposted 25 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Big Data • Information Technology
Oversee the design of connectivity ASICs, coordinating with engineering teams and ensuring timing closure and physical design tasks are met.
Top Skills: CadencePerlPythonSynopsysSystem VerilogTclVerilog
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