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The Principal Digital Design Engineer will architect and implement complex digital designs for connectivity solutions, oversee micro-architecture and RTL implementation, and mentor junior engineers.

Lead optical test engineering for integrated optical-electrical interconnects: define test strategy, validate performance and reliability, support manufacturing test deployment, manage cross-functional teams, drive automation and yield improvements, and ensure standards and customer requirements are met.

Lead end-to-end static timing analysis (STA) and timing closure for complex connectivity SoCs from RTL through sign-off. Develop/validate SDC/MMMC constraints, define I/O timing budgets, run multi-corner/multi-mode STA, apply sign-off methodologies at TSMC 7nm+, generate timing ECOs, and collaborate with RTL, physical design, verification, and IP teams to ensure full-chip timing convergence.

The Physical Design Manager will lead a team to implement connectivity ASICs, handling execution from RTL to GDSII, while ensuring design quality and mentoring engineers.

The role involves leading Static Timing Analysis for complex AI connectivity silicon, driving methodologies, collaborating cross-functionally, and mentoring engineers.

Debug and integrate firmware for Ethernet retimers/gearboxes, triage lab and field failures, fix embedded C/C++ firmware, support customer bring-up, and develop features for SERDES, link training, equalization, and diagnostics.