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Manage office operations including domestic and international travel arrangements, company events, space planning, facility management, records and reports, investor relations support, calendar management, and special projects while leading the administrative team to keep the onsite office organized and efficient.

Develop and troubleshoot embedded system software for ARM-based AI vision products (network cameras, ADAS, robotics). Provide customer technical support, system optimization, kernel/driver development, multimedia capture/encoding, and project support from evaluation through mass production.

Lead enterprise application strategy and governance for ERP, HRIS, CRM, Finance, and Supply Chain systems. Oversee full application lifecycle, ensure SOX and data‑privacy compliance, partner with security and audit, manage global teams and vendors, optimize TCO and drive user adoption while reporting results to executive leadership.

Lead global ISV ecosystem strategy for Ambarella Edge AI platforms: define priority use cases, recruit and onboard ISVs, enable solution validation with cross-functional teams, and drive go‑to‑market deployment and ecosystem growth across Smart Cities, Industrial, Retail, Robotics, and Automotive.

Develop, optimize, and maintain embedded Linux drivers and BSPs for Ambarella SoCs (USB, Ethernet, NAND/NOR, SD/eMMC, PCIe). Upgrade Linux kernels, evaluate system performance, support global customers, collaborate cross-functionally, and produce technical documentation.

Design and develop hardware-aware optimization toolchains for computer vision and ISP models, apply pruning/quantization and other techniques, port models to Ambarella platforms, research emerging optimization methods, and provide customer support for model deployment.

Provide pre- and post-sales technical support for AIoT/edge vision customers: integrate Linux SDKs, deploy AI on edge devices, reproduce and debug system issues, liaise between customers and SoC/firmware/platform teams, guide evaluations and performance tuning, and support production ramp and product validation.

Design and execute verification plans for complex SoCs/IPs using SystemVerilog/UVM, build testbenches, assertions and coverage models, collaborate with architects, designers and post-silicon teams, and ensure design correctness and reliability.

Optimize, quantize, prune and deploy computer-vision deep learning models (PyTorch) onto Ambarella SoC/CVflow. Train and validate models, profile performance on target hardware, implement optimizations, build preprocessing and inference tooling, troubleshoot the model garden, and create tutorials. Collaborate using C/C++ and Python and follow modern software development practices.

Perform full-chip and block-level physical design and verification for low-power AI SoCs from netlist to GDSII, including floorplanning, place-and-route, STA, ECO implementation, signal integrity and EM/IR analysis, and LVS/DRC/DFM physical verification.