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The Senior ASIC Verification Engineer will lead RTL verification processes for ARM SoCs, develop test plans, and oversee functional verification while collaborating with cross-functional teams.

As an ASIC Verification Engineer, you will lead RTL SoC verification, develop test plans, and collaborate with various teams to ensure successful chip validation.

Design and manage end-to-end ML pipelines for cybersecurity, using LLMs and transformers to detect and mitigate threats (ransomware). Implement BMC-level and data-center protections, perform behavioral anomaly detection, and optimize models for edge deployment. Stay current on research and translate AI security research into practical solutions.

Perform block- and subsystem-level ASIC physical implementation from netlist to GDS: floorplanning, placement, CTS, routing, timing closure, power and PPA optimization, physical verification, ECOs, signoff, and automation via Tcl/Python while collaborating with RTL/DFT/DV teams.

Lead and execute ASIC backend implementation from RTL handoff through tapeout. Own floorplanning, power/plaus, placement, CTS, routing, timing closure, ECOs, and signoff. Define physical verification/signoff methodology, debug complex signoff issues, drive automation and shift-left practices, and coordinate contractors, vendors, and cross-functional teams to meet tapeout quality.

Lead operations engineering functions for semiconductor manufacturing, oversee project collaborations, ensure product quality, and manage supply chain communications.