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Join Axiado as an ASIC Design Engineer to work on Smart Edge SoCs for network/systems control and IIoT. Responsibilities include micro-architecture design, RTL coding, synthesis, timing closure, and collaboration with various teams. Must have 8+ years of experience in RTL logic design, Verilog expertise, and familiarity with interface protocols.

Join Axiado, a company focused on AI-enhanced security processors. As an ASIC Verification Engineer, you will work on RTL SoC/Subsystem verification of ARM based SoCs using industry-standard methodologies like UVM, Portable Stimulus, and Formal verification flows. Responsibilities include test plan development, RTL verification, performance verification, system use-case verification, and collaboration with various teams. Requires 8+ years of experience in UVM verification and proficiency in multiple languages and protocols.

Architect System-on-Chips for next-generation infrastructure products, develop platform specifications, collaborate with hardware and software developers, and drive standards in the industry.